View VS6724Q0FB_4130701.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

VS6724
2 Megapixel single-chip camera module
Preliminary Data
Features

1600H x 1200V active pixels Class leading 30 fps UXGA progressive scan 2.2 m pixel size, 1/3.8 inch optical format Quad-element plastic lens, F# 3.2, 52 horizontal field of view 8.0 x 8.0 x 5.55 mm ultra low profile fixed focus camera module with embedded passives RGB Bayer color filter array Integrated 10-bit ADC Integrated digital image processing functions, including defect correction, lens shading correction, image scaling, interpolation, sharpening, gamma correction and color space conversion Embedded hardware JPEG compression (4:2:0 or 4:2:2) delivering 30 fps streaming performance Embedded camera controller for automatic exposure control, automatic white balance control, black level compensation, 50/60 Hz flicker cancelling, flashgun support. Fully programmable frame rate and output derating functions Low power 30 fps up to SVGA for video capture ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, YUV (YCbCr) 4:0:0, RGB 565, RGB 444, JPEG, Bayer 10-bit or Bayer 8bit output formats 8-bit parallel video interface, horizontal and vertical syncs, 80 MHz (max) clock Two-wire serial control interface On-chip PLL, 6.5 to 27 MHz clock input Analog power supply, from 2.4 V to 3.0 V Separate I/O power supply, 1.8 V or 2.8 V levels

Integrated power management with power switch, automatic power-on reset and powersafe pins Low power consumption, ultra low standby current 24-pin 8.0 mm x 8.0 mm x 5.55 mm shielded socket option
Applications

Mobile phone, videophone PDA, toys Medical Biometry Bar code reader Lighting control

Description
The VS6724 is a UXGA resolution CMOS imaging device designed for low power systems, particularly mobile phone applications. Manufactured using ST 0.18 m CMOS Imaging process, it integrates a high-sensitivity pixel array, digital image processor and camera control functions.

July 2007
Rev 1
1/118
www.st.com
1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
VS6724
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Imaging pipe diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sensor array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 2.3.2 Sensor mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Horizontal mirror and vertical flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Recovery engine (RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 Channel offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Channel gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Lens shading compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bayer scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Cropping module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Defect correction 1 & 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Spatial noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5
Color engine (CE block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 Color matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Aperture correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Special effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 YCbCr conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6
Video compression module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.1 2.6.2 2.6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 JPEG compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JPEG squeeze controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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VS6724 2.6.4 2.6.5
Contents FIFO control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JPEG output as a conventional frame . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7 2.8
Microprocessor functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.1 Operational mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Video pipe context configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.8.1 2.8.2 2.8.3 Video pipe setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ViewLive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.9
Output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.9.1 2.9.2 2.9.3 2.9.4 2.9.5 2.9.6 Image size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Line / frame blanking data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 YCbCr 4:2:2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 YCbCr 4:0:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 RGB and Bayer 10 bit data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bayer 8-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.10
Data synchronization methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 Embedded codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Mode 1 (ITU656 compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Embedded synchronization EXT-CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VSYNC and HSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pixel clock (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.11
Timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.11.1 2.11.2 2.11.3 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PLL operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3
Host communication - IC control interface . . . . . . . . . . . . . . . . . . . . . 41
3.1 3.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Detailed overview of the message format . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1 3.2.2 3.2.3 3.2.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Start (S) and Stop (P) conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Index space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3
Types of messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1 3.3.2 Random location, single data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Current location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Contents 3.3.3 3.3.4 3.3.5 3.3.6
VS6724 Random location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Multiple location read stating from the current location . . . . . . . . . . . . . 48 Multiple location read starting from a random location . . . . . . . . . . . . . 49
4
Programming model and register description . . . . . . . . . . . . . . . . . . . 50
4.1 4.2 Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.1 4.2.2 4.2.3 Register interpreter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 User interface register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 6
Optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Chip enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 IC slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Parallel data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7 8 9 10 11
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 User precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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VS6724
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 JPEG data embedded markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ITU656 embedded synchronization code definition (even frames). . . . . . . . . . . . . . . . . . . 33 ITU656 embedded synchronization code definition (odd frames). . . . . . . . . . . . . . . . . . . . 34 CSI - embedded synchronization code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Register naming prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Device parameters [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Device parameters [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Host interface manager status [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Run mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Mode setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PipeContext0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PipeContext1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ViewLive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ViewLive status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Video timing parameter host inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Video timing parameter FP inputs (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Video timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Frame dimension parameter host inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Static frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Static frame rate status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Automatic frame rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Exposure controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Exposure algorithm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Exposure status [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 White balance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 White balance constrainer controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Image stability [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Sensor setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ExpSensor constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Flash control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Flash status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Lens shading correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Defect correction 1 controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Defect correction 2 controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Interpolation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 color matrix dampers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sRGB color matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Peaking control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 RGB to YCbCr matrix manual control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Gamma manual control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Fade to black . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Dither control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 NoRA controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64.
VS6724
Special effects control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 JPEG image characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Supply specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Typical current consumption - sensor mode UXGA - JPEG UXGA@ 30 fps . . . . . . . . . . 105 Typical current consumption - sensor mode UXGA - JPEG UXGA @ 15 fps . . . . . . . . . 106 Typical current consumption - sensor mode UXGA scaled QVGA RGB565 @ 15 fps. . . 106 Typical current consumption - sensor analogue binning SVGA- scaled QVGA RGB565 @ 15 fps106 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Serial interface voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Parallel data interface timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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VS6724
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Imaging pipe block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sensor array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Scaling of Bayer image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Crop controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Color matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 QCLK options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JPEG Compression image size to squeeze value relationship. . . . . . . . . . . . . . . . . . . . . . 20 JPEG frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 State machine at power -up and user mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ViewLive frame output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Standard Y Cb Cr data order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Y Cb Cr data swapping options register bYCbCrSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 YCbCr 4:0:0 format encapsulated in ITU stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 RGB and Bayer data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bayer 8 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ITU656 frame structure with even codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CSI 2 frame structure (VGA example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CSI frame structure (VGA example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 HSYNC timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VSYNC timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 QCLK options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Qualification clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Read message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Detailed overview of message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Device addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SDA data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Internal register index space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Random location, single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Current location, single read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16-bit index, 8-bit data random index, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16-bit index, 8-bit data multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Multiple location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Multiple location read starting from a random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 System / Host view of VS6724 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Voltage level specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SDA/SCL rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Parallel data output video timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Package outline socket module VS6724 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Package outline socket module VS6724 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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Overview
VS6724
1
1.1
Overview
Description
The VS6724 is a UXGA resolution CMOS imaging device designed for low power systems, particularly mobile phone applications. Manufactured using ST 0.18 m CMOS Imaging process, it integrates a high-sensitivity pixel array, digital image processor and camera control functions. The VS6724 is capable of streaming UXGA video up to 30 fps JPEG and up to 15 fps with ITU-R BT.656-4 YCbCr 4:2:2 format. It supports 1.8 V or 2.8 V interface and requires a 2.4 to 3.0 V analog power supply. Typically, the VS6724 can operate as a 2.8 V single supply camera or as a 1.8 V interface / 2.8 V supply camera. The integrated PLL allows for low frequency system clock, and flexibility for successful EMC integration. An input clock is required in the range 6.5 MHz to 27 MHz. The VS6724 camera module uses ST's second generation "SmOP2" packaging technology: the sensor, lens and passives are assembled, tested and focused in a fully automated process, allowing high volume and low cost production. The device contains an embedded video processor and delivers fully color processed images at up to 30 fps UXGA JPEG, or up to 30 fps SVGA YCbCr 4:2:2. The video data is output over an 8-bit parallel bus in JPEG (4:2:2 or 4:2:0), RGB, YCbCr or Bayer formats and the device is controlled via an IC interface. The VS6724 also includes a wide range of image enhancement functions, designed to ensure high image quality, these include:

Automatic exposure control Automatic white balance Lens shading compensation Defect correction algorithms Interpolation (Bayer to RGB conversion) Color space conversion Sharpening Gamma correction Flicker cancellation NoRA noise reduction algorithm Intelligent image scaling Special effects
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VS6724
Overview
1.2
Signal description
The VS6724 has 20 electrical connections which are described in Table 1. The package details and electrical pinout of the flex connector are shown in Figure 45 on page 115 and Figure 46 on page 116. Table 1.
Pad name GND HSYNC VSYNC SCL CLK SDA VDD AVDD PCLK CE DO5 DO4 GND DO3 DO2 DO1 DO0 DO6 DO7 FSO
Signal description
Type PWR OUT OUT IN IN I/O PWR PWR OUT IN OUT OUT PWR OUT OUT OUT OUT OUT OUT OUT Ground(1) Horizontal synchronization output Vertical synchronization output IC clock input Master clock input - 6.5MHz to 27MHz IC data line Digital supply Analogue supply Pixel qualification clock Chip enable signal active HIGH Data output D5 Data output D4 Ground(1) Data output D3 Data output D2 Data output D1 Data output D0 Data output D6 Data output D7 Flash output VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 1.8 V OR 2.8 V 2.4 V to 3.0 V VDD VDD VDD VDD Description Reference voltage
1. The two GND pins are connected together on the device substrate.
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Functional description
VS6724
2
Functional description
The VS6724 simplified block diagram is shown in Figure 1, with the following main blocks:

UXGA-sized pixel array Video pipe Statistics gathering unit Clock generator Microprocessor Video timing generator Simplified block diagram
SDA SCL
Figure 1.
CLK
Clock Generator
IC Interface IC
CE VDD GND
RESET VREG
Microprocessor
Video Timing Generator
Statistics Gathering
AVDD GND UXGA Pixel Array Video Engine
Bypass
Video Compressor (JPEG engine)
Bypass
FSO Output Coder
Bypass
VSYNC HSYNC PCLK D[0:7]
2.1
Operation
A video timing generator controls a UXGA-sized pixel array to produce raw Bayer images. The analogue pixel information is digitized and passed into the video pipe. The video pipe contains a number of different functions (explained in detail later). At the end of the video pipe, data is output to the host system over an 8-bit parallel interface along with qualification signals. The whole system is controlled by an embedded microprocessor that is running firmware stored in an internal ROM. The external host communicates with this microprocessor over an IC interface. The microprocessor does not handle the video data itself but is able to control all the functions within the video pipe. Real-time information about the video data is gathered by a statistics engine and is available to the microprocessor. The processor uses this information to perform real-time image control tasks such as automatic exposure control.
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VS6724
Functional description
2.2
Imaging pipe diagram
The details of the imaging pipe are shown in Figure 2. The main functions contained within this diagram are detailed in this chapter.
Figure 2.
Imaging pipe block diagram
Sensor array Bayer Recovery engine Channel gains & offsets Bayer scaling Stats. gathering
AE & AWB engine
Lens shading Defect correction Noise reduction
Intermediate Bayer data
Host
Color reconstruction (Interpolation, alias) Front end
Color matrix Gamma correction Scaler
Colorspace conversion & JPEG compression
Output formatter Color engine
RGB, YCbCr, JPEG
Aperture correction
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Functional description
VS6724
2.3
Sensor array
The VS6724 physical pixel array is 1616 x 1216 pixels (see Figure 3), with a pixel size of 2.2 m by 2.2 m. The image size read from the array is mode dependent. For UXGA mode the image size read from the array is 1608x1208. For SVGA mode it is 1616x1208. Figure 3. Sensor array
4 Dummy Rows 4 Border Rows
4 Dummy Columns 4 Border Columns
4 Border Columns 4 Dummy Columns
1200 pixels
1208 pixels
Visible array 1600 x 1200 pixels (1608x1208 including borders)
4 Border Rows 4 Dummy Rows 1600 pixels 1608 pixels 1616 pixels
2.3.1
Sensor mode control
The VS6724 can operate it's sensor array in two modes controlled by register SensorMode within Mode setup.
SensorMode_UXGA - the full array can be read out at 30 fps and the VS6724 can achieve: - - - 30 fps JPEGs up to UXGA 30 fps YCbCr or RGB up to SVGA 15 fps YCbCr or RGB over SVGA
SensorMode_SVGA_analogue binning - this is a reduced power mode which uses the full array and a technique of analogue binning output SVGA at up to 30 fps.
2.3.2
Horizontal mirror and vertical flip
The image data output from the VS6724 can be mirrored horizontally or flipped vertically (or both).
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1216 pixels
VS6724
Functional description
2.4
Recovery engine (RE)
The RE is used to process raw Bayer input from the sensor array to an intermediate Bayer which is correctly white balanced and noise reduced, and can be supplied to the interpolation engine.
2.4.1
Channel offsets
To achieve the desired black level of Bayer pixel data it is often necessary to apply an offset to the data. This module provides the functionality to apply color channel dependent offset on active pixel data, i.e. not dark or black data.
2.4.2
Channel gains
Color dependent gains are applied to active pixel data within this module as part of the automatic white balance function. The gain inputs are re-synchronized to the first active line.
2.4.3
Lens shading compensation
The lens shading is used to compensate for attenuation in the optical signal caused by primary and micro lens roll off. The module uses internal counters to determine the input pixel position in terms of imaging array, to which it applies a simple polynomial gain function. This gain is dependent on two coefficients which are system specific.
2.4.4
Bayer scaling
The RE architecture includes an optional Bayer scaler/smoothing module which produces a Bayer image fully compatible with existing image reconstruction techniques. The scaling factor is fixed at downscale-by-3 (in both x & y), with the basic principle of subsampling from successive 3x3 blocks to produce a pseudo-Bayer pattern (2x2 Bayer pattern generated from 6x6 Bayer input as illustrated in Figure 4). This module is intended for use during viewfinder modes to provide a lower power (and reduced quality) image for display on LCD.
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Functional description Figure 4. 1 2 3 4 5 6 (a) Q1 Q2 Scaling of Bayer image
VS6724
ABCDEF
Q3
Q4
(b)
(c)
(d) a) b) c) d) is a 6x6 pixel section of a Bayer patterned pixel array. shows four 3x3 pixel regions which divide the 6x6 pixel array into quarters. shows the pixels in each quarter used to calculate the sub-sampled pixel (and the spatial positioning of the sub-sampled pixel shown by the dashed colored line) shows the final sub-sampled 2x2 Bayer data
The sub-sampled pixel value is the average value of the specific color pixels in each quarter. Smoothing is required in order to regulate the data rate through the image reconstruction chain so as to match any system bandwidth limits.
2.4.5
Cropping module
The VS6724 cropping module can be used to define a window of interest within the full UXGA array size, with all pixels falling outside this window of interest appearing as blanking. The crop block is also used by the scaler to allow configuration of certain output frame dimensions. The user can set a start location and the required output size. Figure 5 shows the example with of the crop.
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VS6724 Figure 5. Crop controls
Sensor array horizontal size
Functional description
uwManualCropHorizontalStart Sensor array vertical size uwManualCropVerticalStart Cropped ROI uwManualCropVerticalSize
uwManualCropHorizontalSize FFOV
2.4.6
Zoom
The zoom function found in the pipe context control sections can be used to achieve a continuous zoom by simply selecting the commands zoom_in, zoom_out and zoom_stop. It is also possible to perform a single step of zoom by selecting Zoom_step_in and Zoom_step_out. It is possible to zoom between the sensor size selected and the output size (the output size must be smaller that the sensor mode size, UXGA or SVGA).
2.4.7
Pan
It is possible to pan left, right, up and down when the output size selected is smaller than the sensor size selected (if the output size selected equals the sensor mode size then no pan can take place). The pan step size in both the horizontal and vertical directions are selectable.
2.4.8
Derating
The VS6724 contains an internal derating module. This is designed to reduce the peak output data rate of the device by spreading the data over the whole frame period and allowing a subsequent reduction in output clock frequency. The maximum achievable derating factor is x400 for an equivalent scale factor of x20 downscale. As a general rule the allowable derating factor is equal to the square of the scaling factor.
Note:
The interline period is not guaranteed to be consistent for all derating ratios. This means the host capture system must be able to cope with use of the sync signals or embedded codes rather than relying on fixed line counts.
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Functional description
VS6724
2.4.9
Defect correction 1 & 2
The input to the defect correction filters is a 5x5 pixel matrix from which a centre pixel and a neighborhood of 8 pixels is extracted. The 8 pixel neighborhood is used to determine the validity of the corresponding centre pixel. This is achieved using the ranked output of a Batcher-Banyan sort architecture. The defect correction filters perform both detection and weighted correction on all data. Defect correction 1 is weighted to work horizontally and vertically. Defect correction 2 is weighted to operate on the diagonal elements.
2.4.10
Spatial noise reduction
The noise reduction module implements an algorithm based on the human-visual system and adaptive pixel filtering that reduces perceived noise in an image whilst maintaining areas of high definition.
2.4.11
Interpolation
The interpolation module converts Bayer pixel data to RGB and applies an anti-alias filter to the data. It also generates the sharp data used in the aperture correction block.
2.5
Color engine (CE block)
The role of the CE is to process the RGB data from the recovery engine into a specific format requested by the host, e.g. RGB565 for LCD display, or YCbCr for the JPEG encoder.
2.5.1
Color matrix
A matrix color correction transform is performed on the outputs of the scaler, the matrix is detailed in Figure 6. Figure 6. Color matrix
rcof00 rcof10 rcof20 rcof01 rcof11 rcof21 rcof02 rcof12 rcof22
The matrix equations are: Ro = Rin.rcof00 + Gin.rcof01 + Bin.rcof02 Go = Rin.rcof10 + Gin.rcof11 + Bin.rcof12 Bo = Rin.rcof20 + Gin.rcof21 + Bin.rcof22
Note:
The neutral-preserving ("eigen-grey") property of the matrix can be achieved by ensuring the matrix rows sum to unity.
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VS6724
Functional description
2.5.2
Aperture correction
The aperture correction module is used to add a certain amount of sharpening to the scaled RGB, it can be programmed to reduce as the light level drops. The aperture correction module also includes a function known as coring which allows control of the minimum magnitude which any edge on the image must exceed before sharpening is applied. This ensures that small edges such as noise are not amplified by the sharpening. The coring can be programmed to increase as the light level drops.
2.5.3
Special effects
The special effects module is used to apply simple transforms onto the input data. The supported effects are: Black and White, Hue, Sepia, Negative, Antique, sketch, caricature and Emboss. There are also a number of color effects which can only be applied to YCbCr data.
2.5.4
Gamma correction
The gamma module is a gain curve applied to each of the three image components from the sharpening module. The shape of the gain curve is fully programmable.
2.5.5
YCbCr conversion
This module performs color space conversion from RGB to YCbCr. It is used to control the contrast and color saturation of the output image as well as the fade to black feature.
2.5.6
Dither
The dither block is used in RGB modes to reduce contouring in the image when the data is truncated to lower ranges. This is achieved by determining the error introduced by truncation and adding/subtracting this residual energy to/from the subsequent pixel.
2.6
Video compression module
The JPEG encoder receives YCbCr data from the image reconstruction engine and encodes it using baseline sequential JPEG technique. It outputs a standard JPEG data stream with all the required markers and segments required by decoders.
2.6.1
Features

Supports YCbCr 422 as input data format. Converts YCbCr 422 to 420 format internally, format selectable. Baseline ISO/ IEC 10918-1 JPEG compliance. Programmable quantization tables. Capable of streaming the UXGA image at a rate of 30 frames per second. Manual / automatic compression control via scaled quantization tables. Automatic compression control targeted at file size and/or peak bit-rate. Progressive high-frequency roll-off option for increased compression. Intraframe rate-control via zig-zag sequence truncation.
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Functional description
VS6724
Quantizer
Quantizer scales the DCT coefficients with programmable luminance and chrominance Qtables. These Q-tables are programmed according to image characteristics, and modified by the squeeze setting. The larger the squeeze setting, the more severe the quantization and the greater the compression achieved. Squeeze values can be manually set via the 8-bit register user_squeeze, or automatically set, and dynamically adjusted, by the autosqueeze module.
Entcoder16
The entcoder16 (entropy coder with 16-bit output) converts the quantized data stream to a symbol stream, including differential encoding of DC samples and run-length encoding of zero-valued AC samples according to the JPEG standard, and finally Huffman-encodes the symbol stream using hardwired baseline JPEG tables to compress the image. It also includes the JPEG header and embeds restart interval markers (if requested by nonzero restartinterval setting) as per the JPEG standard.
Autosqueeze
Autosqueeze is the VC's in-built dynamic compression control system. It adjusts the squeeze parameter based on measurements of two key criteria derived from the previous frame: output file size, and FIFO fullness. Squeeze is subsequently driven iteratively towards the optimal value, satisfying the two conditions: 1. 2. FIFO stability, i.e. fullness has not exceeded a user-defined dead-zone, AND output file size <= a user-defined target.
2.6.2
JPEG compression
At the simplest level the video compressor has one control which is the Squeeze setting: this tells the system how hard to compress. A change in compression is achieved by scaling the quantization tables. Figure 7. QCLK options
Firmware control
Control Squeeze bOIFCLK ratio
UYV 422 to 420 YUV 422
Video compression engine
JPEG output FIFO JPEG
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VS6724
Functional description The FIFO shown in the figure above is being constantly monitored with fixed break points, if the FIFO fill state passes one of these break points the squeeze value is increased or decreased. The amount of data in the FIFO is dependant on a number of factors

The squeeze factor set The complexity of the scene The speed at which the FIFO is being emptied (bOIFClkRatio)
2.6.3
JPEG squeeze controls
The strength of compression or the level of squeeze operated on the image (and therefore the quality of the final image) can be controlled in two ways via the bJpegSqueezeSettings register (note each context can be set independently); bJpegSqueezeSettings0 0x00 SET_USER_SQUEEZE_MODE 0x01 SET_AUTO_SQUEEZE_MODE In auto squeeze mode, the JPEG compression engine is trying to achieve a target file size and constantly changes the compression ratio. This is the preferred mode when using the output JPEG to create a video, or in preview mode. wJpegTargetFileSize {0x03c3, 0x03c4}: Input required size in KBytes In user squeeze mode, the JPEG compression engine will use a constant level of squeeze. This is recommended when trying to capture a high quality image and for snapshot or flashgun modes. For ease of use, the level of squeeze can be adjusted for each pipe context between a high, medium or low level. The value of these squeeze settings can be configured by using the following registers: bJpegImageQuality0 0x00 High quality. Value set in bHiSqueezeValue {0x2508} 0x01 Medium quality. Value set in MedSqueezeValue {0x250a} 0x02 Low quality. Value set in bLowSqueezeValue {0x250c} It is also possible to select between the YCbCr formats input to the video compression engine: bJpegImageFormat 0x00 YCbCr 422 0x01 YCbCr 420
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Functional description Figure 8. JPEG Compression image size to squeeze value relationship
Image size to squeeze relationship
1800 1600 1400 1200 Image size KB 1000 800 600 400 200 0
6 10 5 11 5 12 5 65 75 85 15 25 35 45 55 95
VS6724
Scene1 Scene2 Scene3 Scene4 Scene5 Scene6 Scene7 Scene8 Scene9 Scene10 Scene11 MEAN
Squeeze value
2.6.4
FIFO control
The rate which the FIFO is emptied (and therefore the output PCLK frequency) can be controlled using the bOIFClkRatio register. Changing the FIFO readout rate will in turn change the FIFO's fullness and therefore the squeeze factor used. Section 2.11.2: PLL operation on page 39 describes the calculations for PCLKmax frequency. This frequency is divided by the bOIFClkRatio to give the max JPEG PCLK output from the device: bOIFClkRatio {0x2514} 1. 2. 3. 4. 5. 6. PCLK is 2 times slower PCLK is 4 times slower PCLK is 8 times slower PCLK is 16 times slower PCLK is 32 times slower PCLK is 64 times slower
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VS6724
Functional description
2.6.5
JPEG output as a conventional frame
To keep compatibility with conventional frame format, the JPEG frame is output in a series of packets targeted to look like image lines. The Hsync envelopes each packet (line) of data and the Vsync envelopes the complete frame. The start of the frame is indicated by a transition of the Vsync and Hsync. This will occur when the output FIFO has accumulated enough JPEG data for the first line (default line size 512 = 1KBytes). When this line is output, it will then output blocks of blank data (16Byte blocks) until the next 512Bytes of data is available. The number of bytes per line can be programmed using the following registers, both 16 bit registers should be programmed with the same value:

wLineLength {MSB 0x2511, LSB 0x2512} default = 512 wThres {MSB 0x251b, LSB 0x251c}
Note:
The number of PCLKs in a line is equal to 2 x the line length and the maximum line length is 2K.
In most cases the JPEG data will not fill the last line of data and padding data is added after the JPEG end of image marker FFD9h filling the remainder of the last line. Note that it is possible that the JPEG data will exactly fill the line and no padding is required. The value of padding bytes can be programmed using the following registers, both registers should be programmed with the same value;

bJPEG_FILL_VAL {0x23b4} default = 0xA5 bJPEG_PADDING {0x23b6}
It is not possible to control the timing of the Vsync and Hsync signals in JPEG mode. You can however change the polarity of the signals and select if the Hsync is present or not during the interframe period. PCLK can be made to be present only during active JPEG data, and therefore not present during the interline or interframe periods. The rising edge of PCLK is always half clock delayed from both Hsync and Vsync.
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Functional description Figure 9. JPEG frame
Padding data at the end of the JPEG stream
VS6724
Beginning of JPEG stream(FF D8)
JPEG packet size programmable
JPEG data End of JPEG FF D9 PCLK End of JPEG stream
HSYNC
VSYNC
Packet dispatching depends on the image content. This results in a variable blanking duration.
JPEG packet data
Padding data 0xA5 (Programmable)
Note:
The minimum inter-packet (line) blanking time is 16 clock cycles, and is always a multiple of 16 clock cycles
Table 2. JPEG data embedded markers
Marker function Start of image Define Quantization tables State of frame for baseline Define Huffman Tables Start of Scan End of image SOF DQT DCT SOF DHT SOS End of image Name FFD8 FFDB FFC0 FFC4 FFDA FFD9 Value
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VS6724
Functional description
2.7
Microprocessor functions
The microprocessor inside the VS6724 handles the IC communication with the host processor. From this communication it allows the host control over the device via the User interface registers. Dark calibration: The microprocessor uses information from the array to ensure that the optimal and consistent `black' level is achieved from the output. Automatic exposure control: Using the information output by the statics gathering engine the appropriate exposure settings for the scene is calculated and using a combination of exposure control, analogue gain and digital gain the device will outputs a correctly exposed image. The host can program the exposure target within a range of EV values or can control the system manually setting a known Exposure time, analogue gain and digital gain. Flicker cancellation: The 50/60 Hz flicker frequency present in many lighting sources is visible when the integration time is not a integer multiple of this frequency. The VS6724 will adjust the integration time to ensure that the flicker effect is minimized. Note that flicker is present when using a integration time shorter than the period of the lighting frequency (less than 8.333 ms for 60 Hz, and less than 10 ms for 50 Hz). Automatic white balance: Using the information output by the statics gathering engine the microprocessor adjusts the gains applied to the individual color channels in order to achieve a correctly color balanced image. In addition to the standard white balance operation a constrainer operates on this information which ensures that the white balance achieved fits within the expected color temperature of real life illuminants. Frame rate control: VS6724 contains a firmware based programmable timing generator. This automatically designs internal video timings, PLL multipliers, clock dividers etc. to achieve a target frame rate with a given input clock frequency. Optionally an automatic frame rate controller can be enabled. This system examines the current exposure status and adapts the frame rate based on this information. This function is typically useful in low-light scenarios where reducing the frame rate extends the useful integration period. This reduces the need for the application of analog and digital gain and results in better quality images. Active noise management: The microprocessor is able to modify certain video pipe functions according to the current exposure settings determined by the automatic exposure controller. The main purpose of this is to improve the noise level in the system under low lighting conditions. Functions which `strength' is reduced under low lighting conditions (e.g. aperture correction) are controlled by `dampers'. Functions which `strength' is increased under low lighting conditions are controlled by `promoters'. The fade to black operation is also controlled by the microprocessor Fade to Black: Using programmable levels the microprocessor will fade the output signal to black, this ensures that under the darkest conditions when the image is not of sufficient quality the device will output black. This operation is achieved by scaling the RGB to YCbCr matrix.
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Functional description
VS6724
2.7.1
Operational mode control
The microprocessor allows high level control of the modes in which the VS6724 can operate, this avoids the need for the host to be concerned with the complexity of controlling the timing or power management during mode changes.
Figure 10. State machine at power -up and user mode transitions
Supplies turned-on & CE pin LOW Supplies Off Supplies turned-off
Power-Down
Supplies turned-off
CE pin LOW Standby Uninitialised CE pin HIGH
State Machine at power-up I2C controlled user mode transitions
1
It is possible to enter any of the user modes direct from the uninitialised state via an I2C command
Stop Mode
Snapshot
Pause Mode
Flashgun
Note; Depending on the snapshot exit transition settings the device will revert to RUN or PAUSE state automatically after snapshot
Run Mode
Host initiated state changes System state changes
The power down mode is entered and exited by driving the hardware CE signal. Transitions between all other modes are initiated by IC transactions from the host system or automatically after time-outs.
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VS6724
Functional description Power Down/Up: The power down state is entered when CE is pulled low or the supplies are removed. During the power-down state (CE = logic 0)

The internal digital supply of the VS6724 is shut down by an internal switch mechanism. This method allows a very low power-down current value. The device input / outputs are fail-safe, and consequently can be considered high impedance. The digital supplies must be on and stable. The internal digital supply of the VS6724 is enabled by an internal switch mechanism. All internal registers are reset to default values by an internal power on reset cell.
During the power-up sequence (CE = logic 1)

Figure 11. Power up sequence
POWER DOWN VDD (1.8V/2.8V) AVDD (2.8V) CE t3 CLK SDA SCL t5 Constraints: t1 >= 0 ns t2 >= 0 ns t3 >= 0 ns t4 >= 200 s t5 >= 7 ms (based on 12 MHz external clock frequency, delay is inversely proportional to external clock. Max delay for 6 MHz = 14 ms.) low level command(0xC003): enable clocks t4 t1 t2 standby uninitialised mode
setup commands
STANDBY mode: The VS6724 enters STANDBY mode when the CE pin on the device is pulled HIGH. Power consumption is very low, most clocks inside the device are switched off. In this state IC communication is possible when CLK is present and when the microprocessor is enabled. All registers are reset to their default values. The device I/O pins have a very highimpedance. Uninitialised = RAW: The initialize mode is defined as supplies present, the CE signal is logic 1 and the microcontroller clock has been activated. During initialize mode the device firmware may be patched. This state is provided as an intermediary configuration state and is not central to regular operation of the device. The analogue video block is powered down, leading to a lower global consumption
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Functional description
VS6724
STOP mode: This is a low power mode. The analogue section of the VS6724 is switched off and all registers are accessed over the IC interface. A run command received in this state automatically sets a transition through the Pause state to the run mode. If a STOP command is issued while streaming an incomplete frame may be generated, it is recommended that a Pause command is issued and a timeout set in bTimeToPowerdown to force an automatic transition to STOP. The analogue video block is powered down, leading to a lower global consumption. Pause mode: In this mode all VS6724 clocks are running and all registers are accessible but no data is output from the device. The device is ready to start streaming but is halted. This mode is used to set up the required output format before outputting any data. The analogue video block is powered down, leading to a lower global consumption
Note:
The PowerManagement register can be adjusted in PAUSE mode but has no effect until the next RUN to PAUSE transition.
RUN mode: This is the fully operational mode. In running mode the device outputs a continuous stream of images, according to the set image format parameters and frame rate control parameters. The image size is derived through downscaling of the UXGA image from the pixel array. ViewLive: this feature allows different sizes, formats and reconstruction settings to be applied to alternate frames of data, while in run mode. Snapshot mode: The device can be configured to output a single frame according to the size, format and reconstruction settings in the relevant video pipe context. In normal operation this frame will be output, once the exposure, white balance and dark-cal systems are stable. To reduce the latency to output, the user may manually override the stability flags. The snapshot mode command can be issued in either Run or Stop mode and the device will automatically return previous state after the snapshot is taken. The snapshot mode must not be entered into while ViewLive is selected. FLASHGUN mode: In flashgun mode, the array is configured for use with an external flashgun. A flash is triggered and a single frame of data is output and the device automatically switches to Pause Mode. VS6724 supports the following flashgun configurations:

Torch Mode - user can manually switch on/off the FSO IO pin via a register setting. Independent of mode. Pulsed Mode - the flash output is synchronized to the image stream. There are two options available: - - - - Pulsed flash with snapshot. Device outputs a single frame synchronized to flash. Pulsed flash with viewfinder. Device outputs a flash pulse synchronized to a single frame in the image stream. In the pulsed mode there are two possible pulse configurations: Single pulse during the interframe period when all image lines are exposed. This is suitable for SCR and IGBT flash configurations. The falling edge of the pulse can be programmed to vary the width of the pulse. Single pulse over entire integration period of frame. This is suitable for LED flash configurations.
-
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VS6724
Functional description
Mode transitions
Transitions between operating modes are normally controlled by the host by writing to the Host interface manager control register. Some transitions can occur automatically after a time out. If there is no activity in the Pause state then an automatic transition to the Stop state occurs. This functionality is controlled by the Power management register, writing 0xFF disables the automatic transition to Stop. The users control allows a transition between Stop and Run, at the state level the system will transition through a Pause state.
2.8
2.8.1
Video pipe context configuration
Video pipe setup
The VS6724 has a single video pipe, the control of this pipe can be loaded from either of two possible setups Pipecontext0 and PipeContext1;
PipeContext0 and PipeContext 1, control the operations shown below: Image size Zoom control Pan control Crop control Image format (YCbCr 4:2:2, RGB565, etc....) Image controls (Contrast, Color saturation, Horizontal and vertical flip)
2.8.2
Context switching
In normal operation, it is possible to control which pipe context is used and to switch between contexts without the need to stop streaming, the change will occur at the next frame boundary after the change to the register has been made. For example this function allows the VS6724 to stream an output targeting a display (e.g. QQVGA RGB 444) then switch to capture an image (e.g. UXGA JPEG) with no need to stop streaming or enter any other operating mode. It is important to note the output size selected for both pipe context must be appropriate to the sensor mode used, i.e. to configure PipeContext0 to QQVGA and PipeContext1 to UXGA the sensor mode must be set to UXGA. The register Mode setup allows selection of the pipe context, by default the PipeContext0 is used.
2.8.3
ViewLive operation
ViewLive is an option which allows a different pipe context to be applied to alternate frames of the output data. The controls for VIewLive function are found in the register bank where the fEnable register allows the host to enable or disable the function and the binitialPipecontext register selects which pipe context is output first.
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Functional description
VS6724
When ViewLive is enabled the output data switches between PipeContext0 and PipeContext 1 on each alternate frame. Figure 12. ViewLive frame output format
Frame output
Active Video Pipe context0
Interline Blanking
Interframe Blanking
Active Video Pipe context1
Interline Blanking
Interframe Blanking
2.9
2.9.1
Output formats
Image size
An output frame consists of a number of active lines and a number of interframe lines. Each line consists of embedded line codes (if selected), active pixel data and interline blank data. Note that by default the interline blanking data is not qualified by the PCLK and therefore is not captured by the host system. The image size can be either the full output from the sensor, depending on sensor mode, or a scaled output, The output image size can be chosen from one of 9 pre-selected sizes or a manual image size can be used. The VS6724 supports the following data formats:

JPEG (4:2:2, 4:2:0) YCbCr 4:2:2 YCbCr 4:0:0 RGB565 RGB444 (encapsulated as 565) RGB444 (zero padded) Bayer 10-bit Bayer 8-bit
The required data format is selected using the bdataFomat control found in the pipe context registers. The various options available for each format are controlled using the bRgbsetup and bYCbCrSetup registers found in the Dither control registers.
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VS6724
Functional description
2.9.2
Line / frame blanking data
The values which are output during line and frame blanking are an alternating pattern of 0x10 and 0x80 by default. These values may be changed by writing to the BlankData_MSB and BlankData_LSB registers in the Dither control bank.
2.9.3
YCbCr 4:2:2 data format
YCbCr 422 data format requires 4 bytes of data to represent 2 adjacent pixels. ITU601-656 defines the order of the Y, Cb and Cr components as shown in Figure 13.
Figure 13. Standard Y Cb Cr data order
HSYNC SIGNAL
EAV Code
START OF DIGITAL ACTIVE LINE
8 1 F 0 0 X Cb 00 F00Y
Y
Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
4-data packet
The VS6724 bYCbCrSetup register can be programmed to change the order of the components as follows: Figure 14. Y Cb Cr data swapping options register bYCbCrSetup
Components order in 4-byte data packet 1st 2nd 3rd Y Cb Y Cr Cb Y Cr Y Y Cr Y Cb Bit [0] Cb first Bit [1] Y first
4th Cr Y Cb Y
1 DEFAULT 0 1 0
1 1 0 0
2.9.4
YCbCr 4:0:0
The ITU protocol allows the encapsulation of various data formats over the link. The following data formats are also proposed encapsulated in ITU601-656 protocol:
YCbCr 4:0:0 - luminance data channel
This is done as described in Figure 15. In this output mode the output data per pixel is a single byte. Therefore the output PCLK and data rate is halved. It is possible to reverse the overall bit order of the component through a register programming.
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Functional description
VS6724
Note:
False synchronization codes are avoided in the LSByte by adding or subtracting a value of one, dependent on detection of a 0 code or 255 code respectively.
Figure 15. YCbCr 4:0:0 format encapsulated in ITU stream
START OF DIGITAL ACTIVE LINE
EAV code F 0 0XDDDDDDDDDD F 0 0 Y 0 1 2 3 4 5 6 7 8 9 ..................
Pixel2
Pixel3
Pixel4
Pixel5
Pixel6
Pixel7
Pixel8
Pixel9
Pixel1
YCbCr 4:0:0
F00X F00Y
Pixel10
..................
where:
Pixeln = Yn[7:0]
See Dither control for user interface control of output data formats.
2.9.5
RGB and Bayer 10 bit data formats
The VS6724 can output data in the following formats:

RGB565 RGB444 (encapsulated as RGB565) RGB444 (zero padded) Bayer 10-bit
Note:
Pixels in Bayer 10-bit data output are defect corrected, correctly exposed and white balanced. Any or all of these functions can be disabled.
In each of these modes 2 bytes of data are required for each output pixel. The encapsulation of the data is shown in Table 16.
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VS6724 Figure 16. RGB and Bayer data formats (1) RGB565 data packing Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3
Functional description
2 B2
1 B1
0 B0
R4 R3 R2 R1 R0 G5 G4 G3 second byte (2) RGB 444 packed as RGB565 Bit 7 6 5 4 3 1 2 1 0 Bit
G2 G1 G0 B4
B3
first byte
7 G0
6 1
5 0
4 B3
3 B2
2 B1
1 B0
0 1
R 3 R2 R1 R0
G3 G2 G1
second byte (3) RGB 444 zero padded Bit 7 0 6 0 5 0 4 0 3 2 1 0 Bit 7 6 5
first byte
4
3
2 B2
1 B1
0 B0
R3 R2 R1 R 0
G3 G2 G1 G0 B3 first byte
second byte (4) Bayer 10-bit Bit 7 1 6 0 5 1 4 0 3 1 2 0 1 b9 0 b8 Bit 7 b7 6 b6 5 b5
4 b4
3 b3
2 b2
1 b1
0 b0
second byte
first byte
Manipulation of RGB data
It is possible to modify the encapsulation of the RGB data in a number of ways:

swap the location of the RED and BLUE data reverse the bit order of the individual color channel data reverse the order of the data bytes themselves
Dithering
An optional dithering function can be enabled for each RGB output mode to reduce the appearance of contours produced by RGB data truncation. This is enabled through the DitherControl register.
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Functional description
VS6724
2.9.6
Bayer 8-bit
The ITU protocol allows the encapsulation of various data formats over the link. The following data formats are also proposed encapsulated in ITU601-656 protocol:
Truncated from 10-bit
The output is shown in Figure 17. In this output mode a single byte is output data per pixel, therefore the output PCLK and data rate is half that of the 10bit modes. It is possible to reverse the overall bit order of the individual Bayer pixels through a register programming.
Note:
False synchronization codes are avoided in the LSByte by adding or subtracting a value of one, dependent on detection of a 0 code or 255 code respectively.
Figure 17. Bayer 8 output
START OF DIGITAL ACTIVE LINE
EAV Code F 0 0XDDDDDDDDDDDD F00Y012301230123
Pixel11
where:
Pixel1
Pixel3
Pixel5
Pixel7
8-bit Bayer
F00XL L L LL L L L L LL L F 0 0 Y S S S SS S S S S SS S B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11
LSBn = Bayern[7:0]
2.10
Data synchronization methods
External capture systems can synchronize with the data output from VS6724 in one of two ways: 1. 2. Synchronization codes are embedded in the output data Via the use of two additional synchronization signals: VSYNC and HSYNC
Both methods of synchronization can be programmed to meet the needs of the host system.
2.10.1
Embedded codes
The embedded code sequence can be inserted into the output data stream to enable the external host system to synchronize with the output frames. The code consists of a 4-byte sequence starting with 0xFF, 0x00, 0x00. The final byte in the sequence depends on the mode selected. Two types of embedded codes are supported by the VS6724: Mode 1 (ITU656) and Mode 2. The bSyncCodeSetup register is used to select whether codes are inserted or not and to select the type of code to insert. When embedded codes are selected each line of data output contains 8 additional clocks: 4 before the active video data and 4 after it.
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Pixel9
VS6724
Functional description
Prevention of false synchronization codes
The VS6724 is able to prevent the output of 0xFF and/or 0x00 data from being misinterpreted by a host system as the start of synchronization data. This function is controlled the bCodeCheckEnable register.
2.10.2
Mode 1 (ITU656 compatible)
The structure of an image frame with ITU656 codes is shown in Figure 18. Figure 18. ITU656 frame structure with even codes
Line 1
SAV 80
Frame of image data
EAV 9D
Line 480 SAV AB EAV B6
Frame blanking period
The synchronization codes for odd and even frames are listed in Table 3 and Table 4. By default all frames output from the VS6724 are EVEN. It is possible to set all frames to be ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in theDither control register bank. Table 3. ITU656 embedded synchronization code definition (even frames)
Name SAV EAV SAV (blanking) EAV (blanking) Description Line start - active Line end - active Line start - blanking Line end - blanking 4-byte sequence FF 00 00 80 FF 00 00 9D FF 00 00 AB FF 00 00 B6
Line blanking period 33/118
Functional description Table 4. ITU656 embedded synchronization code definition (odd frames)
Name SAV EAV SAV (blanking) EAV (blanking) Description Line start - active Line end - active Line start - blanking Line end - blanking
VS6724
4-byte sequence FF 00 00 C7 FF 00 00 DA FF 00 00 EC FF 00 00 F1
2.10.3
Embedded synchronization EXT-CSI
The structure of a CSI image frame is shown Figure 19. Figure 19. CSI 2 frame structure (VGA example)
FS Line 1
LS
LE
Line 480
FE
Frame blanking period
For CSI, the synchronization codes are as listed in Table 5. Table 5. CSI - embedded synchronization code definition
Name LS LE FS FE Line start Line end Frame Start Frame End Description 4-byte sequence FF 00 00 00 FF 00 00 01 FF 00 00 02 FF 00 00 03
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Line blanking period
Frame of image data
VS6724
Functional description
CSI logical DMA channels
The purpose of logical channels is to separate different data flows which are interleaved in the data stream, in the case of the VS6724 this allows the identification of the pipe context used for an image frame. The DMA channel identifier number is directly encoded in the 4byte CSI embedded sync codes. The receiver can then monitor the DMA channel identifier and de-multiplex the interleaved video streams to their appropriate DMA channel. The bChannelID register can have the value 0 to 6. The DMA channel identifier must be fully programmable to allow the host to configure which DMA channels the different video data stream use.
Logical channel control
The channel identifier is a part of CSI synchronization code, upper four bits of last byte of synchronization code. Figure 20. CSI frame structure (VGA example) illustrates the synchronization code with logical channel identifiers. Figure 20. CSI frame structure (VGA example)
32-bit embedded ITU-CSI sync code
F
F
0
0
0
0
DC LC
DMA Channel Number Valid channels = 0 to 6
Line code 0x0 = Line Start 0x1 = Line End 0x2 = Frame Start 0x3 = Frame End
2.10.4
VSYNC and HSYNC
The VS6724 can provide two programmable hardware synchronization signals: VSYNC and HSYNC. The position of these signals within the output frame can be programmed by the user or an automatic setting can be used where the signals track the active video portion of the output frame regardless of its size.
Horizontal synchronization signal (HSYNC)
The HSYNC signal is controlled by the bHSyncSetup register. The following options are available:

enable/disable select polarity all lines or active lines only manual or automatic
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Functional description
VS6724
In automatic mode the HSYNC signal envelops all the active video data on every line in the output frame regardless of the programmed image size. Line codes (if selected) fall outside the HSYNC envelope as shown in Figure 21. Figure 21. HSYNC timing example
hsync=0
hsync=1
BLANKING DATA
ACTIVE VIDEO DATA
EAV Code
FF 00 00 XY 80 10 80 10 80 10
SAV Code
80 10 FF 00 00 XY D0 D1 D2 D3 D0 D1 D2 D3
EAV Code
D2 D3 FF 00 00 XY
If manual mode is selected then the pixel positions for HSYNC rising edge and falling edge are programmable. The pixel position for the rising edge of HSYNC is programmed in the bHSyncRising registers. The pixel position for the falling edge of HSYNC is programmed in the bHSyncFalling registers.
Vertical synchronization (VSYNC)
The VSYNC signal is controlled by the bSyncSetup register. The following options are available:

enable/disable select polarity manual or automatic
In automatic mode the VSYNC signal envelops all the active video lines in the output frame regardless of the programmed image size as shown in Figure 22.
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VS6724 Figure 22. VSYNC timing example
Functional description
BLANKING
V=0 V=1
ACTIVE VIDEO
vsync
BLANKING
V=0 V=1
ACTIVE VIDEO
If manual mode is selected then the line number for VSYNC rising edge and falling edge is programmable. The rising edge of VSYNC is programmed in the bVsyncRisingLine registers, the pixel position for VSYNC rising edge is programmed in the bVsyncRisingPixel registers. Similarly the line count for the falling edge position is specified in the bVsyncFallingLine registers, and the pixel count is specified in the bVsyncFallingPixel registers.
2.10.5
Pixel clock (PCLK)
The PCLK signal is controlled by the Dither control register. The following options are available:

enable/disable select polarity select starting phase qualify/don't qualify embedded synchronization codes enable/disable during horizontal blanking
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Functional description Figure 23. QCLK options
data Negative edge Positive edge PCLK Negative edge Positive edge None-active level - Low None-active level - High
D0 D1 D2
VS6724
The YCbCr, RGB and Bayer timings are represented on Figure 24, with the associated qualifying PCLK clock. The output clock rate is effectively halved for the Bayer 8-bit and YCbCr4:0:0 modes where only one byte of output data is required per pixel. Figure 24. Qualification clock
16-bit data output formats - 2 bytes per pixel
Data[7:0] YCbCr
Cbn,n+1
Yn
Crn,n+1
Yn+1
Cbn+2,n+3
PCLK
Data[7:0] Pix0_lsb Pix0_msb Pix1_lsb Pix1_msb Pix2_lsb
RGB565 RGB444
PCLK
Data[7:0] Pix0_lsb Pix0_msb Pix1_lsb Pix1_msb Pix2_lsb
Bayer 10-Bit
PCLK
8-bit data output formats- 1 byte per pixel
Bayer 8-Bit
Data[7:0]
Pix0
Pix1
Pix2
PCLK
Data[7:0] Pix0 Pix1 Pix2
YCbCr 4:0:0
PCLK
In practice the user is likely to require to write some additional setup information prior to receive the required data output.
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VS6724
Functional description
2.11
2.11.1
Timing control
Input clock
The VS6724 requires provision of an external reference clock. The external clock should be a DC coupled square wave and may have been RC filtered. The clock input is fail-safe in power down mode. The VS6724 contains an internal PLL allowing it to produce accurate frame rates from a wide range of input clock frequencies. The allowable input range is from 6.5 MHz to 27 MHz. The external clock frequency must be programmed in the registers found in Table 19: Video timing parameter host inputs.
2.11.2
PLL operation
The VS6724 contains a firmware based programmable timing generator which automatically configures the internal video timing, PLL multipliers, clock dividers to achieve a target operation. The timing generator is controlled and constrained by the required PLL frequency, framerate and scaling factor, this in turn effects the output PCLK frequency.
Timing control
The bSysClkMode register selects the mode in which the system clock manager works,

<0> SYSCLK_MODE_NORMAL <1> SYSCLK_MODE_USER
In normal mode the VS6724 can achieve UXGA at 30 fps and is based on an internal PLL frequency of 260 MHz, the clock management system ensures a maximum output frequency of 80 Mhz (YCbCr). In user mode the VS6724 can be configured to allow the VS6724 to meet the input frequency constraints of a host application. The fpUserPLLCLK register sets the maximum frequency generated by the system clock manager and therefore limits the output frequency and is based on the following equation: fpUserPLLClk = 2 * PCLKmax The PCLKmax may be a limitation on the host and using the following approximate calculation can help work out the framerate achievable with this output PCLK rate; Framerate = PCLKmax / (Image size * data format * 1.10)

Image size = 1600 x 1200 for UXGA sensor mode Image size = 800 x 600 for SVGA sensor mode Data format = 2 for YCbCr 4:2:2, RGB and Bayer10 (as these are 2 Bytes per pixel) Data format = 1 for YCbCr 4:2:0 and Bayer 8 (as these are 1 Byte per pixel) (1.10) is a 10% increase to take into account interline and interframe.
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Functional description
VS6724
2.11.3
Derating
When the scaler is operating the clock manager employs derating to reduce the peak output rate of the device by spreading the data over the full frame period. The derating employed can be found by dividing the input size to the scaler by the output size of the scaler and rounding up to the nearest even number. Example: VGA output scaled from the full UXGA array = 1600x1200 / 640x480 = 6.25 rounded up to the nearest even number = 8, therefore the VGA output is 8 times slower than that for the full UXGA output.
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VS6724
Host communication - IC control interface
3
Host communication - IC control interface
The interface used on the VS6724 is a subset of the IC standard. Higher level protocol adaptations have been made to allow for greater addressing flexibility. This extended interface is known as the V2W interface.
3.1
Protocol
A message contains two or more bytes of data preceded by a START (S) condition and followed by either a STOP (P) or a repeated START (Sr) condition followed by another message. STOP and START conditions can only be generated by a V2W master. After every byte transferred the receiving device must output an acknowledge bit which tells the transmitter if the data byte has been successfully received or not. The first byte of the message is called the device address byte and contains the 7-bit address of the V2W slave to be addressed plus a read/write bit which defines the direction of the data flow between the master and the slave. The meaning of the data bytes that follow device address changes depending whether the master is writing to or reading from the slave. Figure 25. Write message
S DEV ADDR R/W A DATA A 2 Index Bytes DATA A DATA N Data Byte A/A P
`0' (Write)
From Master to Slave
From Slave to Master
For the master writing to the slave the device address byte is followed by 2 bytes which specify the 16-bit internal location (index) for the data write. The next byte of data contains the value to be written to that register index. If multiple data bytes are written then the internal register index is automatically incremented after each byte of data transferred. The master can send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a STOP condition or sends a repeated START (Sr). Figure 26. Read message
S DEV ADDR R/W A DATA A DATA A P
`1' (Read)
1 or more Data Byte
From Master to Slave
From Slave to Master
For the master reading from the slave the device address is followed by the contents of last register index that the previous read or write message accessed. If multiple data bytes are read then the internal register index is automatically incremented after each byte of data
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Host communication - IC control interface
VS6724
read. A read message is terminated by the bus master generating a negative acknowledge after reading a final byte of data. A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation.
3.2
Detailed overview of the message format
1 2 3 4 5 6
Figure 27. Detailed overview of message format
S (Sr)
7-bit device address
R/W
A
8-bit Data
A (A)
P (Sr)
P SDA MSB SCL S or Sr LSB MSB LSB Sr Sr or P
1
2
7
8
9
1
2
7
8
9
START or repeated START condition
Device address
R/W Bit 0 - Write 1 - Read
ACK signal from slave
Data byte from transmitter R/W=0 - Master R/W=1 - Slave
ACK signal from receiver
STOP or repeated Start condition
The V2W generic message format consists of the following sequence: 1. 2. Master generates a START condition to signal the start of new message. Master outputs, MS bit first, a 7-bit device address of the slave the master is trying to communicate with followed by a R/W bit. a) b) 3. 4. R/W = 0 then the master (transmitter) is writing to the slave (receiver). R/W = 1 the master (receiver) is reading from the slave (transmitter).
The addressed slave acknowledges the device address. Data transmitted on the bus a) b) When a write is performed then master outputs 8-bits of data on SDA (MS Bit first). When a read is performed then slave outputs 8-bits of data on SDA (MS Bit First). When a write is performed slave acknowledges data.
5.
Data receive acknowledge a)
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VS6724 b)
Host communication - IC control interface When a read is performed master acknowledges data.
Repeat 4 and 5 until all the required data has been written or read. Minimum number of data bytes for a read =1 (Shortest Message length is 2-bytes). The master outputs a negative acknowledge for the data when reading the last byte of data. This causes the slave to stop the output of data and allows the master to generate a STOP condition. 6. Master generates a STOP condition or a repeated START.
Figure 28. Device addresses
Sensor address 0 0 1 0 0 0 0 R/W
Sensor write address 20H
0
0
1
0
0
0
0
0
Sensor read address 21H
0
0
1
0
0
0
0
1
3.2.1
Data valid
The data on SDA is stable during the high period of SCL. The state of SDA is changed during the low phase of SCL. The only exceptions to this are the start (S) and stop (P) conditions as defined below. (See IC slave interface for full timing specification). Figure 29. SDA data valid
SDA
SCL Data line stable Data valid Data change Data line stable Data valid
3.2.2
Start (S) and Stop (P) conditions
A START (S) condition defines the start of a V2W message. It consists of a high to low transition on SDA while SCL is high. A STOP (P) condition defines the end of a V2W message. It consists of a low to high transition on SDA while SCL is high. After STOP condition the bus is considered free for use by other devices. If a repeated START (Sr) is used instead of a stop then the bus stays busy. A START (S) and a repeated START (Sr) are considered to be functionally equivalent.
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Host communication - IC control interface Figure 30. START and STOP conditions
SDA
VS6724
SCL
S START condition
P STOP condition
3.2.3
Acknowledge
After every byte transferred the receiver must output an acknowledge bit. To acknowledge the data byte receiver pulls SDA during the 9th SCL clock cycle generated by the master. If SDA is not pulled low then the transmitter stops the output of data and releases control of the bus back to the master so that it can either generate a STOP or a repeated START condition. Figure 31. Data acknowledge
SDA data output by transmitter Negative acknowledge (A) SDA data output by receiver Acknowledge (A) SCL clock from master S START condition 1 2 8 9
Clock pulse for acknowledge
3.2.4
Index space
Communication using the serial bus centres around a number of registers internal to the either the sensor or the co-processor. These registers store sensor status, set-up, exposure and system information. Most of the registers are read/write allowing the receiving equipment to change their contents. Others (such as the chip id) are read only. The internal register locations are organized in a 64k by 8-bit wide space. This space includes "real" registers, SRAM, ROM and/or micro controller values.
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VS6724 Figure 32. Internal register index space
Host communication - IC control interface
8 bits 65535 65534 65533 65532
130
16-bit Index / 8-bit Data Format 64k by 8-bit wide index space (Valid Addresses 0-65535)
129 128 127 126 125
4 3 2 1 0
3.3
Types of messages
This section gives guidelines on the basic operations to read data from and write data to VS6724. The serial interface supports variable length messages. A message contains no data bytes or one data byte or many data bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions available are detailed below.

Single location, single byte data read or write. Write no data byte. Only sets the index for a subsequent read message. Multiple location, multiple data read or write for fast information transfers.
Any messages formats other than those specified in the following section should be considered illegal.
3.3.1
Random location, single data write
For the master writing to the slave the R/W bit is set to zero. The register index value written is preserved and is used by a subsequent read. The write message is terminated with a stop condition from the master.
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Host communication - IC control interface Figure 33. Random location, single write
16-bit Index, 8-bit Data, Random Location, Single Data Write
Previous Index Value, K S DEV ADDR R/W A DATA A DATA A DATA Index M A/A P
VS6724
`0' (Write)
INDEX[15:8]
INDEX[7:0]
DATA[7:0]
Index[15:0] value, M From Master to Slave From Slave to Master
DATA[7:0]
S = START condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative acknowledge
3.3.2
Current location, single data read
For the master reading from the slave the R/W bit is set to one. The register index of the data returned is that accessed by the previous read or write message. The first data byte returned by a read message is the contents of the internal index value and NOT the index value. This was the case in older V2W implementations. Note that the read message is terminated with a negative acknowledge (A) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. This is because if the data sent by the slave is all zeros, the SDA line cannot rise, which is part of the stop condition.
Figure 34. Current location, single read
16-bit index, 8-bit data current location, single data read
Previous Index Value, K S DEV ADDR R/W A DATA A P
`1' (Read)
DATA[7:0]
DATA[7:0] From Master to Slave From Slave to Master S = START Condition Sr = repeated START P = STOP Condition A = Acknowledge A = Negative Acknowledge
3.3.3
Random location, single data read
When a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages.
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VS6724
Host communication - IC control interface As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from the master.
Figure 35. 16-bit index, 8-bit data random index, single data read
Previous Index Value, K No Data Write Index M Data Read
S
DEV ADDR R/W A
DATA
A
DATA
A
Sr
DEV ADDR R/W A
DATA
A
P
`0' (Write) INDEX[15:8] INDEX[7:0]
`1' (Read)
DATA[7:0] DATA[7:0]
INDEX[15:0] value, M
From Master to Slave From Slave to Master
S = START Condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative Acknowledge
3.3.4
Multiple location write
For messages with more than 1 data byte the internal register index is automatically incremented for each byte of data output, making it possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte.
Figure 36. 16-bit index, 8-bit data multiple location write
Previous Index Value, K S DEV ADDR R/W A DATA A DATA A Index M DATA A Index (M + N - 1) DATA A/A P
`0' (Write) INDEX[15:8] INDEX[7:0] DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] N Bytes of Data
INDEX[15:0] value, M
From Master to Slave From Slave to Master
S = START condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative acknowledge
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Host communication - IC control interface
VS6724
3.3.5
Multiple location read stating from the current location
In the same manner to multiple location writes, multiple locations can be read with a single read message.
Figure 37. Multiple location read
16-bit Index, 8-bit data multiple location read
Previous Index Value, K S DEV ADDR R/W A DATA A Index K+1 DATA A DATA Index (K + N - 1) A P
`1' (Read)
DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] N Bytes of Data DATA[7:0] DATA[7:0]
From Master to Slave From Slave to Master
S = START condition Sr = repeated START P = STOP Condition
A = Acknowledge A = Negative acknowledge
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3.3.6
VS6724
16-bit Index, 8-bit Data Random Index, Multiple Data Read
Index M Data Read Index (M + N - 1)
Previous Index Value, K No Data Write
S
DEV ADDR R/W A
DATA
A
DATA
A
Sr
DEV ADDR R/W A
DATA
A
DATA
A
P
`0' (Write) INDEX[15:8] INDEX[15:0] value, M DATA[7:0] INDEX[7:0] DATA[7:0]
`1' (Read)
DATA[7:0] DATA[7:0] N Bytes of Data A = Acknowledge A = Negative Acknowledge
From Master to Slave
S = START Condition Sr = repeated START P = STOP Condition
Multiple location read starting from a random location
Figure 38. Multiple location read starting from a random location
Host communication - IC control interface
From Slave to Master
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Programming model and register description
VS6724
4
4.1
Programming model and register description
Programming model
The VS6724 addressable register/memory space is configured as shown below. It consists of four principal areas each of which provides a different function: User Interface: this area starting from address zero provides the user interface. Register reads and writes to this block are passed through the internal micro and processed. All operational control of the device by the host should be performed through these user interface locations.Many of these registers are detailed in Section 4.2: Register description. Registers not listed in this datasheet should be considered as reserved or read-only and should NOT be written to, as this may cause unpredictable results. Hardware registers: provides direct access to hardware registers associated with each functional block of the device. In normal operation, these registers will be accessed under the control of the micro. i.e. they should never be accessed by the host system. However, they may be directly accessed by the host for debug and test purposes. XDATA RAM: provides temporary variable storage for the on-board micro. Patch RAM: provides memory space to download firmware patches and modify device operation. This provides a software update mechanism without the need for a new program ROM. Figure 39. System / Host view of VS6724 memory
FFFF
D800 HARDWARE REGISTERS C000
9FFF 9000 8FFF 8000 4K MCU PATCH RAM 4K MCU XDATA RAM
LEGEND User Interface Hardware Registers XDATA/Patch RAM Blank space
USER INTERFACE
0000
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VS6724
Programming model and register description
4.2
4.2.1
Register description
Register interpreter
Register contents represent different data types as described in Register naming prefix. Table 6. Register naming prefix
Description One Byte unsigned data Two Byte unsigned data One byte data. Only two possible values One Byte data. Specific to module Two byte data. Expect value in Floating Point 16 notation One Byte signed data
Prefix VP_BYTE = ub VP_UINT16 = uw Flag_e(F) = f Enum = e VP_FLOAT = fl VP_INT8 = sb
Registers not listed in this datasheet should be considered as reserved or read-only should NOT be written to, as this may cause unpredictable results. The VS6724 IC write address is 0x20. All IC locations contain an 8-bit byte. However, certain parameters require 16 bits to represent them and are therefore stored in more than 1 location.
Note:
For all 16 bit parameters the MSB register must be written before the LSB register.
The data stored in each location can be interpreted in different ways as shown below. Register contents represent different data types as described in Table 7. Table 7. Data type Description
Single field register 8 bit parameter Multiple field registers - 16 bit parameter Bit 0 of register must be set/cleared Coded register - function depends on value written Float Value
Data type
BYTE UINT_16 FLAG_e CODED FLOAT
Float number format
Float 900 is used in ST co-processors to represent floating point numbers in 2 bytes of data. It conforms to the following structure: Bit[15] = Sign bit (1 represents negative) Bit[14:9] = 6 bits of exponent, biased at decimal 31 Bit[8:0] = 9 bits of mantissa
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Programming model and register description
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4.2.2
Low level control registers
Table 8.
Index MicroEnable Default value 0x1c Used to power up the device CODED <0x1c> initial state after low to high transition of CE pin <0x02> Power enable for all MCU Clock- start device
Low-level control registers LowLevelControlRegisters(1)
0xC003
Purpose Type Possible values DIO_Enable Default value
0x00 Enables the digital I/O of the device CODED <0> IO pins in a high impedance state `Tri-state' <1> IO pins enabled
0xC044
Purpose Type Possible values
1. Can be controlled in all stable states.
Note:
The default values for the above registers are true when the device is powered on, Ext. Clk input is present and the CE pin is high. All other registers can be read when the MicroEnable register is set to 0x02.
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VS6724
Programming model and register description
4.2.3
User interface register description
Device parameters [read only]
Table 9.
Index uwDeviceId 0x0001 (MSByte) Purpose 0x0002 (LSByte) Type 0x0004 Type 0x0006 Type 0x0008 Type 0x000a Type
1. Can be accessed in all stable state.
Device parameters [read only]
DeviceParameters [read only](1)
device id i.e. 724 UINT
bFirmwareVsnMajor BYTE, Silicon cut 1.2 = 0,
bFirmwareVsnMinor BYTE, Silicon cut 1.2 = 8,
bPatchVsnMajor BYTE, Silicon cut 1.2 = 0,
bPatchVsnMinor BYTE, Silicon cut 1.2 = 0,
Host interface manager control
Table 10.
Index bUserCommand Default value Purpose Type 0x0180 <0> UNINITIALISED User level control of operating states CODED
Device parameters [read only]
HostInterfaceManagerControl(1)
<0> UNINITIALISED - powerup default <1> BOOT - the boot command will identify the sensor & setup low level handlers <2> RUN - stream video <3> PAUSE- stop video streaming Possible values <4> STOP - low power mode, analogue powered down <3> SNAPSHOT- grab one frame at correct exposure without flashgun <6> FLASHGUN - grab one frame at correct exposure for flashgun
1. Can be controlled in all stable states
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Programming model and register description
VS6724
Host interface manager status
Table 11.
Index bState Default Value Purpose Type <16>_RAW The current state of the mode manager. CODED <16>_RAW - default powerup state. <33> WAITING_FOR_BOOT - Waiting for ModeManager to signal BOOT event. <34> PAUSED - Booted, the input pipe is idle. <38>WAITING_FOR_RUN - Waiting for ModeManager to complete RUN setup. <49> RUNNING - The pipe is active. <50> WAITING_FOR_PAUSE - The host has issued a PAUSE command. The HostInterfaceManager is waiting for the ModeManager to signal PAUSE processing complete. <64> FLASHGUN - Grabbing a single frame. <80> STOPPED - Low power
Host interface manager status [read only]
HostInterfaceManagerStatus [read only](1)
0x0202
Possible values
bCycles Purpose Type Possible values
1. Can be accessed in all stable states
0x0204
Allows the host to read back a register which indicates that the device is streaming, the output should increment by one on each frame boundary Coded 0 -255
Run mode control
Table 12.
Index fMeteringOn Default Value: 0x0280 Purpose Type Possible values
1. Can be controlled in all stable states
Run mode control
RunModeControl(1)
<1> TRUE If metering is off the Auto Exposure (AE) and Auto White Balance (AWB) tasks are disabled Flag_e <0> FALSE <1> TRUE
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VS6724
Programming model and register description
Mode setup
Table 13.
Index
Mode setup
ModeSetup bNonViewLive_ActivePipeContext (Can be controlled in all stable states) Default Value: <0> PipeContext_0 Select the context used for streaming, can be changed on the fly to switch between contexts on next frame boundary CODED <0> PipeContext_0 <1>PipeContext_1
0x0302
Purpose Type Possible values
bSnapShot_ActivePipeContext (Can be controlled in all stable states) Default Value: 0x0304 Purpose Type Possible values <0> PipeContext_0 Select the context for snapshot mode CODED <0> PipeContext_0 <1>PipeContext_1
SensorMode (Must be configured in STOP mode) Default value 0x0308 Purpose Type Possible values <0>SensorMode_UXGA Select the different sensor mode CODED <0>SensorMode_UXGA <1>SensorMode_SVGA
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Programming model and register description
VS6724
PipeContext0
Table 14.
Index bImageSize0 # Default value Purpose Type <0> ImageSize_UXGA required output dimension. CODED <0> ImageSize_UXGA <1> ImageSize_SXGA <2> ImageSize_SVGA <3> ImageSize_VGA <4> ImageSize_CIF <5> ImageSize_QVGA <6> ImageSize_QCIF <7> ImageSize_QQVGA <8> ImageSize_QQCIF <9> ImageSize_Manual - to use ManualSubSample and ManualCrop controls select Manual mode.
PipeContext0
PipeContext0(1)
0x0380
Possible values
uwManualHSize0 # 0x0383(MSB) 0x0384(LSB) Default value Purpose Type uwManualVSize0 # 0x0387(MSB) 0x0388(LSB) Default value Purpose Type 0x00 if ImageSize_Manual selected, input required manual V size UINT16 0x00 if ImageSize_Manual selected, input required manual H size UINT16
uwZoomStepHSize0 0x038b(MSB) 0x038c(LSB) Default value Purpose Type 0x01 Set the zoom H step UINT16
uwZoomStepVSize0 0x038f(MSB) 0x0390(LSB) Default value Purpose Type 0x01 Set the zoom V step UINT16
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VS6724 Table 14.
Index bZoomControl0 Default value Purpose 0x0392 Type <0> ZoomStop
Programming model and register description PipeContext0 (continued)
PipeContext0(1)
control zoom in, zoom out and zoom stop C <0> ZoomStop <1> ZoomStart_In <2> ZoomStart_Out <3> ZoomStep_in <4> ZoomStep_out
Possible values
uwPanSteplHSize0 0x0395(MSB) 0x0396LSB) Default value Purpose Type uwPanStepVSize0 0x0399(MSB) 0x039a(LSB) Default value Purpose Type bPanControl0 Default value Purpose 0x039c Type <0> Pan_Disable control pandisable, pan right, pan left, pan up, pan down C <0> Pan_Disable <1> Pan_Right <2> Pan_Left <3> Pan_Down <4> Pan_Up 0x00 Set the PanV step UINT16 0x00 Set the pan H step UINT16
Possible values
bCropControl0 Default value 0x039e Purpose Type Possible values <1> Crop_auto Select cropping manual or auto C <0> Crop_manual <1> Crop_auto
uwManualCropHorizontalStart0 0x03a1(MSB) 0x03a2(LSB) Default value Purpose Type 0x00 Set the cropping H start address UINT16
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Programming model and register description Table 14.
Index uwManualCropHorizontalSize0 0x03a5(MSB) 0x03a6(LSB) Default value Purpose Type 0x00 Set the cropping H size UINT16
VS6724
PipeContext0 (continued)
PipeContext0(1)
uwManualCropVerticalStart0 0x03a9(MSB) 0x03aa(LSB) Default value Purpose Type 0x00 Set the cropping Vstart address UINT16
uwManualCropVerticalSize0 0x03ad(MSB) 0x03ae(LSB) Default value Purpose Type bImageFormat0 #(2) Default value Purpose Type <0> ImageFormat_YCbCr_JFIF select required output image format. CODED <0> ImageFormat_YCbCr_JFIF <1> ImageFormat_YCbCr_Rec601 <2> ImageFormat_YCbCr_Custom - to use custom output select required RgbToYCbCr OutputSignalRange from 'PipeContext' page. <3> ImageFormat_YCbCr_400 <4> ImageFormat_RGB_565 <5> ImageFormat_RGB_565_Custom - to use custom output select required RgbToYCbCr OutputSignalRange from 'PipeContext' page. <6> ImageFormat_RGB_444 <7> ImageFormat_RGB_444_Custom - to use custom output select required RgbToYCbCr OutputSignalRange from 'PipeContext' page. <9> ImageFormat_Bayer10_ThroughVP <10> ImageFormat_Bayer8_ThroughVP-- to truncate Bayer data to 8 bits data <11> JPEG 0x00 Set the cropping Vsize UINT16
0x03b0
Possible values
bBayerOutputAlignment0 Default value 0x03b2 Purpose Type Possible values <4> BayerOutputAlignment_RightShifted set Bayer output alignment CODED <4> BayerOutputAlignment_RightShifted <5> BayerOutputAlignment_LeftShifted
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VS6724 Table 14.
Index bContrast0 0x03b4 Default value Purpose Type bcolorSaturation0 0x03b6 Default value Purpose Type bGamma0 Default value 0x03b8 Purpose Type Possible values fHorizontalMirror0 Default Value: 0x03ba Purpose Type Possible values fVerticalFlip0 Default Value: 0x03bc Purpose Type Possible values bChannelD Default value 0x03be Purpose Type Possible values 0x00 0x00 0x00 0x0f gamma settings. BYTE 0 to 31 0x78 0x87
Programming model and register description PipeContext0 (continued)
PipeContext0(1)
contrast control for both YCbCr and RGB output. BYTE
color saturation control for both YCbCr and RGB output. BYTE
Horizontal image orientation flip Flag_e <0> FALSE <1> TRUE
Vertical image orientation flip Flag_e <0> FALSE <1> TRUE
Logical DMA Channel Number BYTE 0 to 6
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Programming model and register description Table 14.
Index bJpegSqueezeSettings Default value Purpose Type 0x03c0 0x00 Select JPEG compression control BYTE
VS6724
PipeContext0 (continued)
PipeContext0(1)
Possible values
<0> User Squeeze mode - Sets the VC squeeze setting as user squeeze (e.g. quality based setting). Low, medium or high quality factor should be set to override these settings <1> Auto Squeeze mode - Sets the VC squeeze setting as auto squeeze (file size based setting). <2> Auto still capture mode - If the host is taking only one still, the engine calibrates and waits for 5-10 frames to work out compression settings to reach optimum squeeze for target file size.
bJpegTargetFileSize 0x03c3(MSB) 0x03c4(LSB) Default value Purpose Type bJpegImageQuality Default value Purpose 0x03c6 Type Possible values 0x00 Sets target JPEG image quality setting for Auto Squeeze mode BYTE <0>High Quality <1> Medium Quality <2> Low Quality 0x02ee (750KB) sets target file size KByte UINT16
bJpegImageFormat Default value 0x03c8 Purpose Type Possible values bMinScalerFactor Default value 0x03cc Purpose Type Possible values 0x10 Sets the minimum scaling factor which can be achieved by the zoom operation, this can be used to limit the max PCLK rate. BYTE 0x00 - 0xff 0x00 Sets image format supplied to JPEG engine BYTE <0>YCbCr 422 <1> YCbCr 420
1. Can be controlled in all stable state. # denotes registers where changes will only be consumed during the transition to a RUN state. 2. It is possible to switch between any YCbCr (422) mode, RGB mode and Bayer 10bit or move between YCbCr 400 and a Bayer8 mode without a requiring a transition to STOP, it is not possible to move between these groups of modes without first a transition to STOP then a BOOT.
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Programming model and register description
PipeContext 1
Table 15.
Index bImageSize1 # Default value Purpose Type <1> ImageSize_UXGA required output dimension. CODED <0> ImageSize_UXGA <1> ImageSize_SXGA <2> ImageSize_SVGA <3> ImageSize_VGA <4> ImageSize_CIF <5> ImageSize_QVGA <6> ImageSize_QCIF <7> ImageSize_QQVGA <8> ImageSize_QQCIF <9> ImageSize_Manual - to use ManualSubSample and ManualCrop controls select Manual mode.
PipeContext1
PipeContext1(1)
0x0400
Possible values
uwManualHSize1 # 0x0403(MSB) 0x0404(LSB) Default value Purpose Type uwManualVSize1 # 0x0407(MSB) 0x0408(LSB) Default value Purpose Type 0x00 if ImageSize_Manual selected, input required manual V size UINT16 0x00 if ImageSize_Manual selected, input required manual H size UINT16
uwZoomStepHSize1 0x040b(MSB) 0x040c(LSB) Default value Purpose Type 0x01 Set the zoom H step UINT16
uwZoomStepVSize1 0x040f(MSB) 0x0410(LSB) Default value Purpose Type 0x01 Set the zoom V step UINT16
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Programming model and register description Table 15.
Index bZoomControl1 Default value Purpose 0x0412 Type <0> ZoomStop control zoom in, zoom out, zoom stop CODED <0> ZoomStop <1> ZoomStart_In <2> ZoomStart_Out <3> ZoomStep_in <4> ZoomStep_out
VS6724
PipeContext1 (continued)
PipeContext1(1)
Possible values
uwPanSteplHSize1 0x0415(MSB) 0x0416(LSB) Default value Purpose Type uwPanStepVSize1 0x0419(MSB) 0x041a(LSB) Default value Purpose Type bPanControl1 Default value Purpose 0x041c Type <0> Pan_Disable control pandisable, pan right, pan left, pan up, pan down C <0> Pan_Disable <1> Pan_Right <2> Pan_Left <3> Pan_Down <4> Pan_Up 0x00 Set the PanV step UINT16 0x00 Set the pan H step UINT16
Possible values
bCropControl1 Default value 0x041e Purpose Type Possible values <1> Crop_auto Select cropping manual or auto C <0> Crop_manual <1> Crop_auto
uwManualCropHorizontalStart1 0x0421(MSB) 0x0422(LSB) Default value Purpose Type 0x00 Set the cropping H start address UINT16
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VS6724 Table 15.
Index uwManualCropHorizontalSize1 0x0425(MSB) 0x0426(LSB) Default value Purpose Type 0x00
Programming model and register description PipeContext1 (continued)
PipeContext1(1)
Set the cropping H size UINT16
uwManualCropVerticalStart1 0x0429(MSB) 0x042a(LSB) Default value Purpose Type 0x00 Set the cropping Vstart address UINT16
uwManualCropVerticalSize1 0x042d(MSB) 0x042e(LSB) Default value Purpose Type bImageFormat1(2) Default value Purpose Type <0> ImageFormat_YCbCr_JFIF select required output image format. CODED <0> ImageFormat_YCbCr_JFIF <1> ImageFormat_YCbCr_Rec601 <2> ImageFormat_YCbCr_Custom - to use custom output select required RgbToYCbCr OutputSignalRange from 'PipeContext' page. <3> ImageFormat_YCbCr_400 <4> ImageFormat_RGB_565 <5> ImageFormat_RGB_565_Custom - to use custom output select required RgbToYCbCr OutputSignalRange from 'PipeContext' page. <6> ImageFormat_RGB_444 <7> ImageFormat_RGB_444_Custom - to use custom output select required RgbToYCbCr OutputSignalRange from 'PipeContext' page. <9> ImageFormat_Bayer10ThroughVP <10> ImageFormat_Bayer8ThroughVP-- to truncate Bayer data to 8 bits data <11> JPEG 4:2:2 0x00 Set the cropping Vsize UINT16
0x0430
Possible values
bBayerOutputAlignment1 Default value 0x0432 Purpose Type Possible values <4> BayerOutputAlignment_RightShifted set Bayer output alignment CODED <4> BayerOutputAlignment_RightShifted <5> BayerOutputAlignment_LeftShifted
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Programming model and register description Table 15.
Index bContrast1 0x0434 Default value Purpose Type bcolorSaturation1 0x0436 Default value Purpose Type bGamma1 Default value 0x0438 Purpose Type Possible values fHorizontalMirror1 Default value 0x043a Purpose Type Possible values fVerticalFlip1 Default value 0x043c Purpose Type Possible values bChannelD Default value 0x043e Purpose Type Possible values 0x00 Logical DMA Channel Number BYTE 0 to 6 0x00 Vertical image orientation flip Flag_e <0> FALSE <1> TRUE 0x00 Horizontal image orientation flip Flag_e <0> FALSE <1> TRUE 0x0f gamma settings. BYTE 0 to 31 0x78 color saturation control for both YCbCr and RGB output. BYTE 0x87 contrast control for both YCbCr and RGB output. BYTE
VS6724
PipeContext1 (continued)
PipeContext1(1)
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VS6724 Table 15.
Index bJpegSqueezeSettings Default value Purpose Type 0x0440 0x00
Programming model and register description PipeContext1 (continued)
PipeContext1(1)
Select JPEG compression control BYTE <0> User Squeeze mode - Sets the VC squeeze setting as user squeeze (e.g. quality based setting). Low, medium or high quality factor should be set to override these settings <1> Auto Squeeze mode - Sets the VC squeeze setting as auto squeeze (file size based setting). <2> Auto still capture mode - If the host is taking only one still, the engine calibrates and waits for 5-10 frames to work out compression settings to reach optimum squeeze for target file size.
Possible values
bJpegTargetFileSize 0x0443(MSB) 0x0444(LSB) Default value Purpose Type bJpegImageQuality Default value Purpose 0x0446 Type Possible values 0x00 Sets target JPEG image quality setting for Auto Squeeze mode BYTE <0>High Quality <1> Medium Quality <2> Low Quality 0x02ee (750KB) sets target file size KByte UINT16
bJpegImageFormat Default value 0x0448 Purpose Type Possible values bMinScalerFactor Default value 0x044c Purpose Type Possible values 0x10 Sets the minimum scaling factor which can be achieved by the zoom operation, this can be used to limit the max PCLK rate. BYTE 0x00 - 0xff 0x00 Sets image format supplied to JPEG engine BYTE <0>YCbCr 422 <1> YCbCr 420
1. Can be controlled in all stable state. # denotes registers where changes will only be consumed during the transition to a RUN state. 2. It is possible to switch between any YCbCr (422) mode, RGB mode and Bayer 10bit or move between YCbCr 400 and a Bayer8 mode without a requiring a transition to STOP, it is not possible to move between these groups of modes without first a transition to STOP then a BOOT.
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Programming model and register description
VS6724
ViewLive control
Table 16.
Index
ViewLive control
ViewLiveControl fEnable (Can be controlled in all stable states) Default value <0> FALSE set to enable the View Live mode. Flag_e <0> FALSE <1> TRUE
0x0480
Purpose Type Possible values
bInitialPipeContext (must be setup in PAUSE or STOP mode) Default value Purpose Type Possible values <0> PipeContext_0 First frame output will be from PipeSetupBank selected by 'bInitialPipeContext'. if ViewLive is enabled the next frame will be from the other PipeContext, otherwise only one PipeContext will be used. CODED <0> PipeContext_0 <1> PipeContext_1
0x0482
ViewLive status [read only]
Table 17.
Index CurrentPipeContext Default value 0x0500 Purpose Type Possible values <0>PipeContext_0 indicates the PipeContext which has most recently been applied to the pixel pipe hardware. CODED <0> PipeContext_0 <1> PipeContext_1
ViewLive status
ViewLiveStatus [read only]
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VS6724
Programming model and register description
Power management
Table 18.
Index bTimeToPowerdown Default value 0x0580 Purpose Type
1. Must be configured in STOP mode
Power management
PowerManagement(1)
0x0f Time (mSecs) from entering Pause mode until the system automatically transitions stop mode. 0xff disables the automatic transition. BYTE
Video timing parameter host inputs
Table 19.
Index
Video timing parameter host inputs
VideoTimingParameterHostInputs(1) uwExternalClockFrequencyNumerator Default value 0x0c The External Clock Frequency configuration must match the frequency supplied to the CLK pin; External clock frequency = uwExternalClockFrequencyDenumerator/ bExternalClockFrequencyDenominator UINT16 The External clock frequency range is 6 to 27, this represents 6MHz to 27 MHz
0x0605(MSByte) 0x0606(LSByte)
Purpose
Type Possible values
bExternalClockFrequencyDenominator 0x0608 Default value Type
1. Should be configured in the RAW state
0x01 BYTE
Video timing parameter FP inputs (read only)
Table 20.
Index
Video timing parameter FP inputs (read only)
VideoTimingParameterFPInputs (read only)(1) uwExternalClockFrequencyMhzNumerator
0x0605(MSByte) 0x0606(LSByte)
Purpose Type
Allows the host to read back the uwExternalClockFrequency FLOAT
1. Can be read in all operating modes
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Programming model and register description
VS6724
Video timing control
Table 21.
Index bSysClkMode Default value 0x0880 Purpose Type Possible values bfpUserPLLClk Default value 0x0883(MSByte) 0x0884(LSByte) Purpose Type Possible values
1. Must be controlled in STOP state
Video timing control
VideoTimingControl(1)
0x00 User selection between using default system clock frequency or selecting this frequency manually CODED <0>Normal - Default PLL frequency <1>user - Manual selection of PLL frequency
0x00 User selectable system clock frequency FLOAT - number of MHz Minimum = 6 Maximum = 270 (Max required for 30fps)
Frame dimension parameter host inputs
Table 22.
Index bLightingFrequencyHz Default value 0x0b80 Purpose Type 0x64 AC Frequency - used for flicker free time period calculations this mains frequency determines the flicker free time period. BYTE
Frame dimension parameter host inputs
FrameDimensionParameterHostInputs(1)
fFlickerCompatibleFrameLength Default value 0x0b82 Purpose Type Possible values
1. Can be controlled in all stable states
<0> FALSE flicker_compatible_frame_length Flag_e <0> FALSE <1> TRUE
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VS6724
Programming model and register description
Static frame rate control
Table 23.
Index uwDesiredFrameRate_Num 0x0c81(MSByte) 0x0c82(LSByte) Default value Purpose Type 0x1e Numerator for the Frame Rate UINT16
Static frame rate control
StaticFrameRateControl(1)
bDesiredFrameRate_Den 0x0c84 Default value Purpose Type
1. Can be controlled in all stable states
0x01 Denominator for the Frame Rate BYTE
Static frame rate status (read only)
Table 24.
Index fprequestedFramerate_Hz 0x0d01(MSByte) 0x0d02(LSByte) Purpose Type
1. Can be controlled in all stable states
Static frame rate status
StaticFrameRatestatus(1)
Shows the existing framerate of the system FLOAT
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Programming model and register description
VS6724
Automatic frame rate control
Table 25.
Index bFrameRateMode Default value Purpose 0x0d80 Type <0> Manual - the system uses the values programmed into the StaticFrameRateControl registers <1> Auto - the system automatically adjusts the framerate between the bUserMinimumFrameRate_Hz and bUserMinimumFrameRate_Hz. 0x00 Defines the mode in which the framerate of the system would work
Automatic frame rate control
AutomaticFrameRateControl(1)
Possible values
bImpliedGainThresholdLow_num 0x0d82 Default value Purpose Type 0x02 Numerator for calculation of low threshold of autoframerate control BYTE
bImpliedGainThresholdLow_den 0x0d84 Default value Purpose Type 0x02 Denominator for calculation of low threshold of autoframerate control. BYTE
bImpliedGainThresholdHigh_num 0x0d86 Default value Purpose Type 0x02 Numerator for calculation of High threshold of autoframerate control BYTE
bImpliedGainThresholdHigh_Den 0x0d88 Default value Purpose Type 0x02 Denominator for calculation of high threshold of autoframerate control BYTE
bUserMinimumFrameRate_Hz Default value 0x0d8a Purpose Type 0x02 Sets the minimum framerate employed when in automatic framerate mode. BYTE
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VS6724 Table 25.
Index
Programming model and register description Automatic frame rate control (continued)
AutomaticFrameRateControl(1) bUserMinimumFrameRate_Hz Default value 0x1e Sets the maximum framerate employed when in automatic framerate mode. BYTE
0x0d8c Purpose Type
bRelativeChange_num 0x0d8e Default value Purpose Type 0x02 Numerator for calculation of relative change in framerate. BYTE
bRelativeChange_den 0x0d90 Default value Purpose Type 0x0e01 0x0e02 0x02 Denominator for calculation of relative change in framerate BYTE
fpImpliedGain (read only) Purpose Type
1. Can be controlled in all stable states
Displays the present value of implied gain FLOAT
Exposure controls
Table 26.
Index bMode Default value Purpose Type 0x1080 <0> AUTOMATIC_MODE Sets the mode for the exposure algorithm CODED <0> AUTOMATIC_MODE - Automatic Mode of Exposure which includes computation of Relative Step <1> COMPILED_MANUAL_MODE - Compiled Manual Mode in which the desired exposure is given and not calculated by algorithm <2> DIRECT_MANUAL_MODE - Mode in which the exposure parameters are input directly and not calculated by compiler <3> FLASHGUN_MODE - Flash Gun Mode in which the exposure parameters are set to fixed values
Exposure controls
ExposureControls(1)
possible values
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Programming model and register description Table 26.
Index bMetering Default value Purpose 0x1082 Type <0> ExposureMetering_flat
VS6724
Exposure controls (continued)
ExposureControls(1)
Weights to be associated with the zones for calculating the mean statistics Exposure Weight could Centered, Backlit or Flat C <0> ExposureMetering_flat - Uniform gain associated with all pixels <1> ExposureMetering_backlit - more gain associated with centre pixels and bottom pixels <2> ExposureMetering_centred - more gain associated with centre pixels
possible values
bManualExposureTime_Num Default value 0x1084 Purpose Type 0x01 Exposure Time for Compiled Manual Mode in seconds. Num/Den gives required exposure time BYTE
bManualExposureTime_Den 0x1086 Default value Type 0x1e BYTE
fpManualFloatExposureTime 0x1089(MSByte) 0x108a(LSByte) Default value Purpose Type 0x59aa (15008) Exposure Time for the Manual Mode. This value is in microseconds. iMiscSettings must be configured FLOAT
fpColdStartDesiredTime_us 0x108d(MSByte) 0x108e(LSByte) Default value Purpose Type 0x59aa (15008) Exposure Time for the that the system will use when entering RUN mode FLOAT
iExposureCompensation Default value 0x1090 Purpose 0x00 Exposure Compensation - a user choice for setting the runtime target. A unit of exposure compensation corresponds to 1/6 EV. Default value according to the Nominal Target of 30 is 0. Coded Value of Exposure compensation can take values from -25 to 12. INT8
Type
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VS6724 Table 26.
Index iMiscSettings Default value Purpose 0x1092 Type 0x00
Programming model and register description Exposure controls (continued)
ExposureControls(1)
Set Bit [6] to use fpManualFloatExposureTime value INT8 0x00 - COMPILED_MANUAL_MODE uses bManualExposureTime_Num and bManualExposureTime_Den 0x40 - COMPILED_MANUAL_MODE uses fpManualFloatExposureTime
Possible Value
uwDirectModeCoarseIntegrationLines 0x1095 (MSByte) 0x1096(LSByte) Default value Purpose Type 0x00 Coarse Integration Lines to be set for Direct Mode UINT16
uwDirectModeFineIntegrationPixels 0x1099(MSByte) 0x109a(LSByte) Default value Purpose Type 0x00 Fine Integration Pixels to be set for Direct Mode UINT16
fpDirectModeAnalogGain 0x109d (MSByte) 0x109e(LSByte) Default value Purpose Type 0x00 Analog Gain to be set for Direct Mode FLOAT
fpDirectModeDigitalGain 0x10a1 (MSByte) 0x10a2(LSByte) Default value Purpose Type 0x00 Digital Gain to be set for Direct Mode FLOAT
uwFlashGunModeCoarseIntLines 0x10a5 (MSByte) 0x10a6(LSByte) Default value Purpose Type 0x00 Coarse Integration Lines to be set for Flash Gun Mode UINT16
uwFlashGunModeFineIntPixels 0x10a9 (MSByte) 0x10aa(LSByte) Default value Purpose Type 0x00 Fine Integration Pixels to be set for Flash Gun Mode UINT16
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Programming model and register description Table 26.
Index fpFlashGunModeAnalogGain 0x10ad (MSByte) 0x10ae(LSByte) Default value Purpose Type 0x00 Analog Gain to be set for Flash Gun Mode FLOAT
VS6724
Exposure controls (continued)
ExposureControls(1)
fpFlashGunModeDigitalGain 0x10b1 (MSByte) 0x10b2(LSByte) Default value Purpose Type 0x00 Digital Gain to be set for Flash Gun Mode FLOAT
fFreezeAutoExposure Default value 0x10b4 Purpose Type possible values <0> FALSE Freeze auto exposure Flag_e <0> FALSE <1> TRUE
fpUserMaximumIntegrationTime Default value 0x10b7 (MSByte) 0x10b8(LSByte) 0x647f (654336) User Maximum Integration Time in microseconds. This control takes in the maximum integration time that host would like to support. This would in turn give an idea of the degree of "wobbly pencil effect" acceptable to Host. FLOAT
Purpose
Type
fpRecommendFlashGunAnalogGainThreshold 0x10bb(MSByte) 0x10bc(LSByte) Default value Purpose Type bAntiFlickerMode Default value Purpose 0x10c0 Type Possible values
1. Can be controlled in all stable states
0x4200 (4) Recommend flash gun analog gain threshold value FLOAT
<0> AntiFlickerMode_Inhibit Anti flicker mode CODED <0> AntiFlickerMode_Inhibit <1> AntiFlickerMode_ManualEnable <2>AntiFlickerMode_AutomaticEnable
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VS6724
Programming model and register description
Exposure algorithm control
Table 27.
Index fpDigitalGainFloor Default value 0x1119(MSByte) 0x111a(LSByte) Purpose Type Possible values 1.0000 Minimum digital gain applied by the auto exposure system FLOAT Min 1.0000, Max 2.50000
Exposure algorithm control
ExposureAlgorithmControl(1)
fpDigitalGainCeiling Default value 0x111d(MSByte) 0x111e(LSByte) Purpose Type Possible values
1. Can be controlled in all stable states
2.5000 Maximum Digital Gain applied by the auto exposure system FLOAT Min 1.0000, Max 2.50000
Exposure status [read only]
Table 28.
Index
Exposure status [read only]
ExposureStatus [read only] uwCoarseIntegrationPending_lines
0x1209(MSByte) 0x120a(LSByte)
Purpose
The course period of time over which every pixel is integrating is a multiple of the number of lines times the number of pixels on the line times the pixel period. These registers show the number of lines of integration which will be used for the next frame. FLOAT
Type 0x120d(MSByte) 0x120e(LSByte)
uwFineIntegrationPending_pixels Purpose Type 0x1211(MSByte) 0x1212(LSByte) The fine period of integration is detailed as a added of FLOAT
fpAnalogGainPending Purpose Type 0x1215(MSByte) 0x1216(LSByte) Minimum digital gain applied by the auto exposure system FLOAT
fpDigitalGainPending Purpose Type 0x1219(MSByte) 0x121a(LSByte) Maximum Digital Gain applied by the auto exposure system FLOAT
fpDesiredExposureTime_us Purpose Type Time in second that the system would like to use for correct exposure FLOAT
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Programming model and register description Table 28.
Index fpCompiledExposureTime_us 0x121d(MSByte) 0x121e(LSByte) Purpose Type Time in second that the system uses FLOAT
VS6724
Exposure status [read only] (continued)
ExposureStatus [read only]
fpFinalDesiredExposureTime_us 0x1285(MSByte) 0x1286(LSByte) Purpose Type Absolute time in second that the system would like to use for correct exposure, this is the value which is used to control the dampers FLOAT
White balance control
Table 29.
Index bWhiteBalanceMode Default value Purpose Type 0x1380 <1> AUTOMATIC For setting Mode of the white balance CODED <0> OFF - No White balance, all gains will be unity in this mode <1> AUTOMATIC - Automatic mode, relative step is computed here <3> MANUAL_RGB - User manual mode, gains are applied manually <4> DAYLIGHT_PRESET - DAYLIGHT and all the modes below, fixed value of gains are applied here. <5> TUNGSTEN_PRESET <6> FLUORESCENT_PRESET <7> HORIZON_PRESET <8> MANUAL_color_TEMP <9> FLASHGUN_PRESET
White balance control
WBControlParameters(1)
possible values
bManualRedGain Default value Purpose 0x1382 Type 0x00 User setting for Red Channel gain BYTE 0 to 255 Applied_Red_Gain = (1 + bManualRedGain / 128) / MinGain Where MinGain = the smallest value from either Applied_Red_Gain, Applied_Green_Gain or Applied_Blue_Gain
possible values
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VS6724 Table 29.
Index bManualGreenGain Default value Purpose 0x1384 Type 0x00
Programming model and register description White balance control (continued)
WBControlParameters(1)
User setting for Green Channel gain BYTE 0 to 255 Applied_Green_Gain = (1 + bManualGreenGain / 128) / MinGain Where MinGain = the smallest value from either Applied_Red_Gain, Applied_Green_Gain or Applied_Blue_Gain
possible values
bManualBlueGain Default value Purpose 0x1386 Type 0x00 User setting for Blue Channel gain BYTE 0 to 255 Applied_Blue_Gain = (1 + bManualBlueGain / 128) / MinGain Where MinGain = the smallest value from either Applied_Red_Gain, Applied_Green_Gain or Applied_Blue_Gain
possible values
bMiscSettings Default value 0x1388 Purpose Type possible values fpFlashRedGain 0x138b (MSByte) 0x138c(LSByte) Default value Purpose Type fpFlashGreenGain 0x138f (MSByte) 0x1390(LSByte) Default value Purpose Type 0x3e00 (1.000) When FLASHGUN_PRESET is selected in bWhiteBalanceMode the fpFlashGreenGain is used. FLOAT 0x3e80 (1.250) When FLASHGUN_PRESET is selected in bWhiteBalanceMode the fpFlashRedGain is used. FLOAT 0x00 Bit [2] fFreezeWhiteBalance BYTE 0x00 - Normal 0x04 - Freeze white balance
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Programming model and register description Table 29.
Index fpFlashBlueGain 0x1393(MSByte) 0x1394(LSByte) Default value Purpose Type
1. Can be controlled in all stable states
VS6724
White balance control (continued)
WBControlParameters(1)
0x3e8a (1.269531) When FLASHGUN_PRESET is selected in bWhiteBalanceMode the fpFlashBlueGain is used. FLOAT
White balance constrainer controls
Table 30.
Index fpRedA 0x1501(MSByte) 0x1502(LSByte) Default value Purpose Type fpBlueA 0x1505(MSByte) 0x1506(LSByte) Default value Purpose Type fpRedB 0x1509(MSByte) 0x150a(LSByte) Default value Purpose Type fpBlueB 0x150d(MSByte) 0x150e(LSByte) Default value Purpose Type 0.281738 Sets location of Ref. B point on constrainer control FLOAT 0.4223636 Sets location of Ref. B point on constrainer control FLOAT 0.4223636 Sets location of Ref. A point on constrainer control FLOAT 0.281738 Sets location of Ref. A point on constrainer control FLOAT
White balance constrainer controls
WhiteBalanceConstrainerControls(1)
fpMaximumDistanceAllowedFromLocus 0x1511(MSByte) 0x1512(LSByte) Default value Purpose Type 0.281738 Sets distance from locus within which the white balance is constrained. FLOAT
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VS6724 Table 30.
Index
Programming model and register description White balance constrainer controls (continued)
WhiteBalanceConstrainerControls(1) fEnableConstrainedWhiteBalance Default value 0.4223636 Maximum Digital Gain applied by the auto exposure system CODED <0> FALSE <1> TRUE
0x1514
Purpose Type Possible values
1. Can be controlled in all stable states
Image stability [read only]
Table 31.
Index fWhiteBalanceStable Default value 0x1800 Purpose Type Possible values fExposureStable Default value 01802 Purpose Type Possible values fStable Default value 0x1808 Purpose Type Possible values 0x00 Consolidated flag to indicate whether the system is stable/unstable CODED <0> Unstable <1> Stable 0x00 Indicated that the exposure system is stable/unstable CODED <0> Unstable <1> Stable 0x00 Indicated that white balance system is stable/unstable CODED <0> Unstable <1> Stable
Image stability [read only]
Image stability [read only]
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Programming model and register description
VS6724
Sensor setup
Table 32.
Index fpRedtilt 0x1885 0x1886 Default value Purpose Type fpGreentilt 0x1889 0x188a Default value Purpose Type fpbluetilt 0x188d 0x188e Default value Purpose Type 0x3e00 An offset can be applied to the Blue data from the sensor array to ensure help match the response of all the color channels BYTE 0x3e00 An offset can be applied to the Green data from the sensor array to ensure help match the response of all the color channels BYTE 0x3e00 An offset can be applied to the Red data from the sensor array to ensure help match the response of all the color channels BYTE
Sensor setup
SensorSetup(1)
bBlackCorrectionOffset Default value 0x1890 Purpose Type
1. Can be controlled in all stable states
0x00 A black correction offset can be added to the sensor pedestal. This maybe adjusted to improve the black level. BYTE
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VS6724
Programming model and register description
ExpSensor constants
Table 33.
Index uwSensorAnalogGainFloor Default value 0x1901(MSByte) 0x1902(LSByte) Purpose Type Possible values. 0x00 Sets the minimum gain that will be used by the auto exposure system. BYTE-Bits [7:0] - NOTE: Bits[16:8 and 3:0] are not used. Min Analogue gain = 256 / (256 - uwSensorAnalogGainFloor)
ExpSensor constants
ExpSensorConstants(1)
uwSensorAnalogGainFloor Default value 0x1905(MSByte) 0x1906(LSByte) Purpose Type Possible values
1. Can be controlled in all stable states
0xd0 Sets the maximum gain that will be used by the auto exposure system. BYTE-Bits [7:0] - NOTE: Bits[16:8 and 3:0] are not used. Max Analogue gain = 256 / (256 - uwSensorAnalogGainFloor)
Flash control
Table 34.
Index bFlashMode Default value Purpose 0x1980 Type Possible values <0> FLASH_OFF Select the flash type and on/off CODED <0> FLASH_OFF <1>FLASH_TORCH <2>FLASH_PULSE
Flash control
FlashControl(1)
uwFlashOffLine 0x1983(MSB) 0x1984(LSB) Default value Purpose Type
1. Can be controlled in all stable states
0x021c (540) In flash_pulse mode, used to control off line UINT16
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Programming model and register description
VS6724
Flash status [read only]
Table 35.
Index fFlashRecommend Default value <0> FALSE This flag is set if the Exposure Control system reports that the image is underexposed and so the flashgun is recommended to the Host controlled by register fpRecommendFlashGunAnalogGainThreshold. It is at the discretion of Host to use it or not for the following still grab. Flag_e <0> FALSE <1> TRUE
Flash status
FlashStatus [read only]
0x1a00
Purpose
Type Possible values
fFlashGrabComplete Default value 0x1a02 Purpose Type Possible values <0> FALSE This flag indicates that the FlashGun Image has been grabbed. Flag_e <0> FALSE <1> TRUE
Lens shading correction
Table 36.
Index uwHorizontalOffsetR 0x1c01 (MSByte) 0x1c02 (LSByte) Default value purpose type 0x00 Controls lens shading Horizontal Offset for red pixels VPIP_UINT16
Lens shading correction
LensShadingcorrection(1)
uwHorizontalOffsetGR 0x1c05 (MSByte) 0x1c06 (LSByte) Default value purpose type Controls lens shading Horizontal Offset for green_red pixels VPIP_UINT16
uwHorizontalOffsetGB 0x1c09 (MSByte) 0x1c0a (LSByte) Default value purpose type Controls lens shading Horizontal Offset for green_blue pixels VPIP_UINT16
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VS6724 Table 36.
Index uwHorizontalOffsetB 0x1c0e (MSByte) 0x1c0f (LSByte) Default value purpose type uwVerticalOffsetR 0x1c11 (MSByte) 0x1c12 (LSByte) Default value purpose type uwVerticalOffsetGR 0x1c15 (MSByte) 0x1c16 (LSByte) Default value purpose type uwVerticalOffsetGB 0x1c19 (MSByte) 0x1c1a (LSByte) Default value purpose type uwVerticalOffsetB 0x1c1e (MSByte) 0x1c1f (LSByte) Default value purpose type iR2RCoefficient Default value 0x1c20 purpose type iR2GRCoefficient Default value 0x1c22 purpose type
Programming model and register description Lens shading correction (continued)
LensShadingcorrection(1)
Controls lens shading Horizontal Offset for blue pixels VPIP_UINT16
Controls lens shading Vertical Offset for red pixels VPIP_UINT16
Controls lens shading Vertical Offset for green_red pixels VPIP_UINT16
Controls lens shading Vertical Offset for green_blue pixels VPIP_UINT16
Controls lens shading Vertical Offset for blue pixels VPIP_UINT16
Controls lens shading R2 component for red pixels. VPIP_INT8
Controls lens shading R2 component for green_red pixels. VPIP_INT8
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Programming model and register description Table 36.
Index iR2GBCoefficient Default value 0x1c24 purpose type iR2BCoefficient Default value 0x1c26 purpose type iR4RCoefficient Default value 0x1c28 purpose type iR4GRCoefficient Default value 0x1c2a purpose type iR4GBCoefficient Default value 0x1c2c purpose type iR4BCoefficient Default value 0x1c2e purpose type Controls lens shading R4 component for blue pixels. VPIP_INT8 0x00 Controls lens shading R4 component for green_blue pixels. VPIP_INT8 Controls lens shading R4 component for green_red pixels. VPIP_INT8 Controls lens shading R4 component for red pixels. VPIP_INT8 Controls lens shading R2 component for blue pixels. VPIP_INT8 Controls lens shading R2 component for green_blue pixels. VPIP_INT8
VS6724
Lens shading correction (continued)
LensShadingcorrection(1)
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VS6724 Table 36.
Index fDisable Default value 0x1c30 purpose type possible values
1. Can be controlled in all stable states
Programming model and register description Lens shading correction (continued)
LensShadingcorrection(1)
0x00 To enable or disable Lens shading block Flag_e <0> VPIP_FALSE <1> VPIP_TRUE
Defect correction 1 controls
Table 37.
Index fDisableFilter Default value 0x1c80 Purpose Type Possible values
1. Can be controlled in all stable state
Defect correction 1 controls
DefectCorrection1Controls(1)
<0> FALSE Disable defect correction 1 Flag_e <0> FALSE <1> TRUE
Defect correction 2 controls
Table 38.
Index fDisableFilter Default value 0x1d00 Purpose Type Possible values
1. Can be controlled in all stable state
Defect correction 2 controls
DefectCorrection 2Controls(1)
<0> FALSE Disable defect correction 2 Flag_e <0> FALSE <1> TRUE
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Programming model and register description
VS6724
Interpolation control
Table 39.
Index bAntiAliasFilterSuppress 0x1d80 Default value Purpose Type
1. Can be controlled in all stable state
Interpolation control
InterpolationControl(1)
0x08 Anti alias filter suppress BYTE
Color matrix dampers
Table 40.
Index fDisable Default value 0x1e00 Purpose Type Possible values fpLowThreshold 0x1e03(MSByte) 0x1e04(LSByte) Default value Purpose Type fpHighThreshold 0x1e07(MSByte) 0x1e08(LSByte) Default value Purpose Type fpMinimumOutput 0x1e0b (MSByte) 0x1e0c(LSByte) Default value Purpose Type
1. Can be controlled in all stable state
color matrix dampers
colorMatrixDamper(1)
<0> FALSE set to disable color matrix damper and therefore ensure that all the color matrix coefficients remain constant under all conditions. Flag_e <0> FALSE <1> TRUE
0x67d1 (2000896) Low Threshold for exposure for calculating the damper slope FLOAT
0x6862 (2498560) High Threshold for exposure for calculating the damper slope FLOAT
0x3acd (0.350098) Minimum possible damper output for the color matrix FLOAT
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VS6724
Programming model and register description
sRGB color matrix
Table 41.
Index fpGinR 0x1e81 (MSByte) 0x1e82(LSByte) Default value Purpose Type fpBinR 0x1e85 (MSByte) 0x1e86 (LSByte) Default value Purpose Type fpRinG 0x1e89 (MSByte) 0x1e8a (LSByte) Default value Purpose Type fpBinG 0x1e8d (MSByte) 0x1e8e (LSByte) Default value Purpose Type fpRinB 0x1e91 (MSByte) 0x1e92 (LSByte) Default value Purpose Type fpGinB 0x1e95 (MSByte) 0x1e96(LSByte) Default value Purpose Type 0x00 Green in Blue element FLOAT 0x00 Red in Blue element FLOAT Blue in Green element FLOAT Red in Green element FLOAT Blue in Red element FLOAT Green in Red element FLOAT
sRGB color matrix
sRGBColorMatrix(1) (2)
1. The diagonal elements of the matrix are calculated such at the sun for each row equal unity 2. Can be controlled in all stable states
87/118
Programming model and register description
VS6724
Peaking control
Table 42.
Index bUserPeakGain 0x1f00 Default value Purpose Type 0x0e controls peaking gain / sharpness applied to the image BYTE
Peaking control
Peaking control(1)
fDisableGainDamping Default value 0x1f02 Purpose Type Possible values <0> FALSE set to disable damping and therefore ensure that the peaking gain applied remains constant under all conditions Flag_e <0> FALSE <1> TRUE
fpDamperLowThreshold_Gain 0x1f05 (MSByte) 0x1f06(LSByte) Default value Purpose Type 0x62ac (350208) Low Threshold for exposure for calculating the damper slope - for gain FLOAT
fpDamperHighThreshold_Gain 0x1f09 (MSByte) 0x1f0a(LSByte) Default value Purpose Type 0x65d1 (10004488) High Threshold for exposure for calculating the damper slope - for gain FLOAT
fpMinimumDamperOutput_Gain 0x1f0d (MSByte) 0x1f0e(LSByte) Default value Purpose Type 0x3d33 (0.799805) Minimum possible damper output for the gain. FLOAT
bUserPeakLoThresh 0x1f10 Default value Purpose Type 0x1e Adjust degree of coring. range: 0 - 63 BYTE
fDisableCoringDamping Default value 0x1f12 Purpose Type Possible values <0> FALSE set to ensure that bUserPeakLoThresh is applied to gain block Flag_e <0> FALSE <1> TRUE
88/118
VS6724 Table 42.
Index bUserPeakHiThresh 0x1f14 Default value Purpose Type 0x30
Programming model and register description Peaking control (continued)
Peaking control(1)
adjust maximum gain that can be applied. range: 0 - 63 BYTE
fpDamperLowThreshold_Coring 0x1f107(MSByte) 0x1f108(LSByte) Default value Purpose Type 0x624a (300032) Low Threshold for exposure for calculating the damper slope - for coring FLOAT
fpDamperHighThreshold_Coring 0x1f1b (MSByte) 0x1f1c(LSByte) Default value Purpose Type 0x656f (900096) High Threshold for exposure for calculating the damper slope - for coring FLOAT
fpMinimumDamperOutput_Coring 0x1f1f (MSByte) 0x1f20(LSByte) Default value Purpose Type
1. Can be controlled in all stable states
0x3a00 (0.2500) Minimum possible damper output for the Coring. FLOAT
89/118
Programming model and register description
VS6724
RGB to YCbCr matrix manual control
Table 43.
Index fRgbToYCbCrManuCtrl Default value 0x2080 Purpose Type Possible values w0_0 0x2083 (MSByte) 0x2084(LSByte) Default value Purpose Type w0_1 0x2087 (MSByte) 0x2088(LSByte) Default value Purpose Type w0_2 0x208b (MSByte) 0x208c(LSByte) Default value Purpose Type w1_0 0x208f (MSByte) 0x2090(LSByte) Default value Purpose Type w1_1 0x2093 (MSByte) 0x2094(LSByte) Default value Purpose Type w1_2 0x2097 (MSByte) 0x2098(LSByte) Default value Purpose Type 0x00 Row 1 Column 2 of YCbCr matrix UINT_16 0x00 Row 1 Column 1 of YCbCr matrix UINT_16 0x00 Row 1 Column 0 of YCbCr matrix UINT_16 0x00 Row 0 Column 2 of YCbCr matrix UINT_16 0x00 Row 0 Column 1 of YCbCr matrix UINT_16 0x00 Row 0 Column 0 of YCbCr matrix UINT_16 <0> FALSE Enables manual RGB to YCbCr matrix Flag_e <0> FALSE <1> TRUE
RGB to YCbCr matrix manual control
RGB to YCbCr matrix (1)
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VS6724 Table 43.
Index w2_0 0x209b (MSByte) 0x209c(LSByte) Default value Purpose Type w2_1 0x209f (MSByte) 0x20a0(LSByte) Default value Purpose Type w2_2 0x20a3(MSByte) 0x20a4(LSByte) Default value Purpose Type YinY 0x20a7 (MSByte) 0x20a8(LSByte) Default value Purpose Type YinCb 0x20ab (MSByte) 0x20ac(LSByte) Default value Purpose Type YinCr 0x20af (MSByte) 0x20b0(LSByte) Default value Purpose Type
1. Can be controlled in all stable states
Programming model and register description RGB to YCbCr matrix manual control
RGB to YCbCr matrix (1)
0x00 Row 2 Column 0 of YCbCr matrix UINT_16
0x00 Row 2 Column 1 of YCbCr matrix UINT_16
0x00 Row 2 Column 2 of YCbCr matrix UINT_16
0x00 Y in Y UINT_16
0x00 Y in Cb UINT_16
0x00 Y in Cr UINT_16
91/118
Programming model and register description
VS6724
Gamma manual control
Table 44.
Index fGammaManuCtrl Default value 0x2100 Purpose Type Possible values bRPeakGamma 0x2102 Default value Purpose Type bGPeakGamma 0x2104 Default value Purpose Type bBPeakGamma 0x2106 Default value Purpose Type bRUnPeakGamma 0x2108 Default value Purpose Type bGUnPeakGamma 0x210a Default value Purpose Type bBUnPeakGamma 0x210c Default value Purpose Type
1. Can be controlled in all stable states
Gamma manual control
GammaManuControl(1)
<0> FALSE Enables manual Gamma Setup Flag_e <0> FALSE <1> TRUE
0x00 Peaked Red channel gamma value BYTE
0x00 Peaked Green channel gamma value BYTE
0x00 Peaked Blue channel gamma value BYTE
0x00 Unpeaked Red channel gamma value BYTE
0x00 Unpeaked Green channel gamma value BYTE
0x00 Unpeaked Blue channel gamma value BYTE
92/118
VS6724
Programming model and register description
Fade to black
Table 45.
Index fDisable Default value 0x2280 Purpose Type 0x2283(MSByte) 0x2284(LSByte) fpBlackValue Default value Purpose Type 0x2287 (MSByte) 0x2288(LSByte) 0x0000 (0.000) Black value FLOAT <0> FALSE Flag_e <0> FALSE <1> TRUE
Fade to black
FadeToBlack(1)
fpDamperLowThreshold Default value Purpose Type 0x6d56 (6995968) Low Threshold for exposure for calculating the damper slope FLOAT
0x228b (MSByte) 0x228c(LSByte)
fpDamperHighThreshold Default value Purpose Type 0x6cdc (11993088) High Threshold for exposure for calculating the damper slope FLOAT
0x228f (MSByte) 0x2290(LSByte)
fpDamperOutput Default value Purpose Type 0x0 (0.0000) Minimum possible damper output. FLOAT
1. Can be controlled in all stable states
Dither control
Table 46.
Index bDither Block control Default value 0x2300 Purpose Type Possible values
1. Can be controlled in all stable state
Dither control
DitherControl(1)
0x00 Control of dither block BYTE 0 -> Control Automatic 1 -> Control Manual
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Programming model and register description
VS6724
Output control
Table 47.
Index bYCbCrSetup Default value Type Purpose 0x2380 0x00 CODED Changes the output order of YCbCr [[0] Cb_Cr_Order 0-> Cr before Cb 1-> Cb before Cr [1] Y_ C order 0-> Cb or Cr first 1-> Y first
Output control
OutputControl(1)
flag bits
bRgbSetup Default value Type Purpose 0x00 CODED Setup the RGB padding and order [0]rgb444_format 0-> zero padding 0x2382 1->not zero padding [3:1] RGB output order 0-> GBR flag bits 1-> RBG 2-> BRG 3-> GRB 4-> RGB 5-> BGR bBlank_Value_1 Default value 0x238c Type Purpose Possible values bBlank_Value_2 Default value 0x238e Type Purpose Possible values 0x80 CODED First Blanking value used during interline & interframe blanking <128> BlankingLSB_Default 0x10 CODED First Blanking value used during interline & interframe blanking <16> BlankingMSB_Default
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VS6724 Table 47.
Index bHSyncSetup Default value Type 0x0b CODED
Programming model and register description Output control (continued)
OutputControl(1)
[0] HSyncSetup_sync_en 1-> enable hsync 0-> disable hsync [1] HSyncSetup_sync_pol 1-> hsync active high 0-> hsync active low [2] HSyncSetup_only_activelines 1-> hsync qualifies only active lines 0-> hsync qualifies active and non active lines, (PCLK will be on for non active lines) [3] HSyncSetup_track_henv 1-> automatic tracking hsync, ensures that the Hsync qualifies from the first active pixel to last active pixel 0 -> programmable rise and fall of the hsync signal
0x2390 flag bits
bVSyncSetup Default value Type 0x07 CODED [0] VSyncSetup_sync_en 0x2392 flag bits 1-> enable vsync 0-> disable vsync [1] VSyncSetup_pol 1-> vsync active high 0-> vsync active low [2] VSyncSetup_2_sel 1-> automatic tracking the vsync, so that it covers from the first active line to last active line 0->manually set the rising and falling of the vsync signal
0x2395MSByte) 0x2396(LSByte)
bHsyncRisingH Default value Type Purpose 0x00 BYTE Operates only when bHSyncSetup bit [3] = 0
0x2399MSByte) 0x239a(LSByte)
bHsyncFallingH Default value Type Purpose 0x00 BYTE Operates only when bHSyncSetup bit [3] = 0
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Programming model and register description Table 47.
Index 0x239d(MSByte) 0x239e(LSByte) bVsyncRisingFine Default value Type Purpose 0x23a1(MSByte) 0x23a2(LSByte) 0x00 BYTE Operates only when bVSyncSetup bit [2] = 0
VS6724
Output control (continued)
OutputControl(1)
bVsyncFallingFineH Default value Type Purpose 0x00 BYTE Operates only when bVSyncSetup bit [2] = 0
0x23a5(MSByte) 0x23a6(LSByte)
bVsyncRisingCoarse Default value Type Purpose 0x00 UINT_16 Operates only when bVSyncSetup bit [2] = 0
0x23a9MSByte) 0x23aa(LSByte)
bVsyncFallingCoarseH Default value Type Purpose bSyncCodeSetup Default value Type 0x01 CODED [0] SyncCodeSetup_ins_code_en 1-> enable embedded codes 0-> disable embedded codes [1] SyncCodeSetup_frame 0=ITU-656, 1 ITU-CSI 0-> ITU-656 codes 1-> ITU-CSI codes [2] SyncCodeSetup_field_bit - ITU-656 only 1-> Next field is odd frame 0-> Next field is even frame [3] SyncCodeSetup_field_tag - ITU-656 only 1-> the sync code for odd and even frames will toggle 0 -> the sync code will be constant for all frames [4] SyncCodeSetup_field_load - ITU-656 only 1-> Load new settings for bits [3:2] 0 -> New settings for bits [3:2] not consumed 0x01 BYTE Operates only when bVSyncSetup bit [2] = 0
0x23ae flag bits
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VS6724 Table 47.
Index bPClkSetup Default value Type 0x05 CODED
Programming model and register description Output control (continued)
OutputControl(1)
[0] PClkSetup_prog_lo 1-> Rising Edge of PCLK 0-> Falling Edge of PCLK [1] PClkSetup_prog_hi 1-> Polarity of PLCK normally high 0-> Polarity of PLCK normally low [2] PClkSetup_sync_en 1-> Enable PCLK during Embedded sync codes 0-> Disable PCLK during Embedded sync codes [3] PClkSetup_hsync_en_n 1-> enable the PCLK outside the HSYNC active period 0-> disable the PCLK outside the HSYNC active period [4] PClkSetup_hsync_en_n_track_internal 1-> use the internal tracked hsync for the qualification of the bit[3] 0-> use the manually set hsync for the qualification of the bit[3] [5] PClkSetup_vsync_n 1-> enable pclk outside VSYNC active period 0-> disable pclk outside VSYNC active period [6] PClkSetup_vsync_n_track_internal 1-> use the internal tracked vsync for the qualification of the bit[5] 0-> use the manually set vsync for the qualification of the bit[5] [7] PClkSetup_freer 1-> Set the PCLK to free run 0 ->Set the PCLK to be controlled fPclkEn Default value 0x23b2 Type Possible values <1> TRUE Flag_e <0> FALSE <1> TRUE
0x23b0 flag bits
1. Changes only consumed during a change to RUN mode
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Programming model and register description
VS6724
NoRA controls
Table 48.
Index fDisable Default value 0x2400 Type Possible values <0> NoraCtrl_auto Flag_e <0> NoraCtrl_auto - switches off NoRA for scaled outputs <1> NoraCtrl_ManuDisable - Always off <2> NoraCtrl_ManuEnable - Always on
NoRA controls
NoRAControls(1)
bUsage 0x2402 Default value Purpose Type BYTE 0x04
fDisableNoroPromoting Default value 0x240a Type Possible values <0> FALSE Flag_e <0> FALSE <1> TRUE
fpDamperLowThreshold 0x240d (MSByte) 0x240e(LSByte) Default value Purpose Type 0x6862 (2498560) Low Threshold for exposure for calculating the damper slope FLOAT
fpDamperHighThreshold 0x2411 (MSByte) 0x2412(LSByte) Default value Purpose Type 0x6a62 (4997120) High Threshold for exposure for calculating the damper slope FLOAT
MinimumDamperOutput 0x2415 (MSByte) 0x2416(LSByte) Default value Purpose Type
1. Can be controlled in all stable states
0x3a00 (0.2500) Minimum possible damper output. FLOAT
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VS6724
Programming model and register description
Special effects control
Table 49.
Index fNegative Default value 0x2480 Purpose Type Possible values fSolarising Default value 0x2482 Purpose Type Possible values fSketch Default value 0x2484 Purpose Type Possible values fEmboss Default value 0x2486 Purpose Type Possible values <0> FALSE Uses mathematical functions to create the effect that the image detail is raised above the surface of the background Flag_e <0> FALSE <1> TRUE <0> FALSE Edges of the image enhanced and output to give the impression of a pencil sketch Flag_e <0> FALSE <1> TRUE <0> FALSE Colors reversed and edges enhanced to give solarizing effect Flag_e <0> FALSE <1> TRUE <0> FALSE INverse of image generated Flag_e <0> FALSE <1> TRUE
Special effects control
SpecialEffectsControl(1)
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Programming model and register description Table 49.
Index fColorEffects Default value Purpose <0> Special effect added to the output image
VS6724
Special effects control (continued)
SpecialEffectsControl(1)
0x2488 Type
0 Normal 1 Red only - Red information preserved, all other color info set to mono 2 Yellow only - Red and Green information preserved, blue info set to mono 3 Green only - Green information preserved, all other color info set to mono 4 Blue only - Blue information preserved, all other color info set to mono 5 Black and white - Monochrome 6 Sepia - to mimic the wet film effect of replacing the silver in black and white print with brown silver sulphide 7 Antique - to mimic the yellowing effect when an old black and white photo ages NOTE; All color effects can operate on YCbCr and JPEG formats but only Sepia and B & W operate when using RGB formats.
1. Can be controlled in all stable states
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VS6724
Programming model and register description
JPEG image characteristics
Table 50.
Index bJPEG_Fill_Val Default value 0x23b4 Purpose Type bJPEG_Padding Default value 0x23b6 Purpose Type bHiSqueezeValue Default value 0x2508 Purpose Type Possible values bMedSqueezeValue 0x2508 Default value Purpose Type bLowSqueezeValue 0x2508 Default value Purpose Type uwLinelength 0x2511 0x2512 Default value Purpose Type 0x0200 Sets the number of bytes of JPEG data are present in each Packet (line), must equal uwThres WORD 0x28 Sets squeeze factor for Low Quality BYTE 0x20 Sets squeeze factor for Medium Quality BYTE 0x18 Sets squeeze factor for HIgh Quality BYTE The Squeeze value can be programmed between the range 6 (Highest quality) to 255 (Low quality) 0xa5 Value of padding bytes inserted at the end of the JPEG data sequence to fill the final packet, must equal bJPEG_Fill_Val BYTE 0xa5 Value of padding bytes inserted at the end of the JPEG data sequence to fill the final packet, must equal bJPEG_Padding BYTE
JPEG image characteristics
JPEGImageCharacteristics(1)
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Programming model and register description Table 50.
Index bOIFCLKRatio Default value Purpose Type 0x1
VS6724
JPEG image characteristics (continued)
JPEGImageCharacteristics(1)
Determines the maximum PCLK output rate for the JPEG data, in relation to the YUV pixel clock frequency BYTE 0 ->PCLK is same frequency YUV pixel clock, for non JPEG //for JPEG 1-> PCLK is 2 times slower
0x2514
2-> PCLK is 4 times slower 3-> PCLK is 6 times slower Possible values 4-> PCLK is 8 times slower 5-> PCLK is 10 times slower 6-> PCLK is 12 times slower 7-> PCLK is 14 times slower 8-> PCLK is 16 times slower 9-> PCLK is 18 times slower 10-> PCLK is 20times slower uwThres Default value 0x0200 Sets the number of bytes of JPEG data are present in each Packet (line), must equal uwLinelength WORD The number of bytes in a line is 2 x the value programmed into this register, the maximum number of bytes in a line is 2KB.
0x251b 0x251c
Purpose Type Possible values
1. Can be controlled in all stable states
102/118
VS6724
Optical specifications
5
Optical specifications
Table 51. Optical specifications(1)
Parameter Optical format Effective focal length Aperture (F number) Horizontal field of view Depth of field TV distortion
1. All measurements made at 23C 2C
Min.
Typ. 1/3.8
Max.
Unit inch
3.7
3.8 3.2 50
3.9
mm
deg. infinity 1 cm %
60 -1
103/118
Electrical characteristics
VS6724
6
6.1
Electrical characteristics
Absolute maximum ratings
Table 52.
Symbol TSTO VDD AVDD
Absolute maximum ratings
Parameter Storage temperature Digital power supplies Analog power supplies Min. -40 -0.5 -0.5 Max. 85 3.3 3.3 Unit C V V
Caution:
Stress above those listed under "Absolute Maximum Ratings" can cause permanent damage to the device. This is a stress rating only and functional operations of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6.2
Operating conditions
Table 53.
Symbol TAF TAN
Supply specifications
Parameter Operating temperature, functional (Camera is electrically functional) Operating temperature, nominal (Camera produces acceptable images) Operating temperature, optimal (Camera produces optimal optical performance) Digital power supplies operating range (@ module pin(1)) Analog power supplies operating range (@ module pin(1)) Min. -30 -25 Typ. 25 25 Max. 70 55 Unit C C
TAO
5 1.7 2.4 2.4
25 1.8 2.8 2.8
30 2.0 3.0 3.0
C V V V
VDD AVDD
1. Module can contain routing resistance up to 5 .
104/118
VS6724
Electrical characteristics
6.3
Note:
Table 54.
Symbol VIL VIL_CLK VIH VOL VOH IIL CIN COUT CI/O
DC electrical characteristics
Over operating conditions unless otherwise specified.
DC electrical characteristics
Description Input low voltage Input low voltage Input high voltage Output low voltage Output high voltage Input leakage current Input pins I/O pins Input capacitance, SCL Output capacitance I/O capacitance, SDA IOL < 2 mA IOL < 4 mA IOH< 4 mA 0 < VIN < VDD TA = 25 C, freq = 1 MHz TA = 25 C, freq = 1 MHz TA = 25 C, freq = 1 MHz 0.8 VDD +/- 10 +/- 1 6 6 8 Test conditions except CLK CLK pin Min. -0.3 -0.3 0.7 VDD Typ. Max. 0.3 VDD 0.5 VDD + 0.3 0.2 VDD 0.4 VDD Unit V V V V V A A pF pF pF
Table 55.
Symbol
Typical current consumption - sensor mode UXGA - JPEG UXGA@ 30 fps
IAVDD Description supply current in power down mode supply current in Standby mode supply current in Stop mode supply current in Pause mode supply current in active streaming run mode Test conditions VDD = 2.8V VDD = 1.8V VDD = 2.8V IVDD Units
IPD Istanby IStop IPause Irun
CE=0, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz
2.34 0.0024 0.0024 0.58 29
0.05 2.41 2.11 51 120
0.07 2.59 2.44 57 135
A mA mA mA mA
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Electrical characteristics Table 56.
Symbol
VS6724
Typical current consumption - sensor mode UXGA - JPEG UXGA @ 15 fps
IAVDD Description supply current in power down mode supply current in Standby mode supply current in Stop mode supply current in Pause mode supply current in active streaming run mode Test conditions VDD = 2.8V VDD = 1.8V VDD = 2.8V IVDD Units
IPD Istanby IStop IPause Irun
CE=0, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz
2.34 0.0024 0.0024 0.58 29
0.05 2.41 1.98 28.5 67
0.07 2.59 2.31 31 73
A mA mA mA mA
Table 57.
Symbol
Typical current consumption - sensor mode UXGA scaled QVGA RGB565 @ 15 fps
IAVDD Description supply current in power down mode Test conditions VDD = 2.8V VDD = 1.8V VDD = 2.8V IVDD Units
IPD Istanby IStop IPause Irun
CE=0, CLK = 12 MHz
2.34 0.0024 0.0024 0.58 29
0.05 2.41 1.93 15.75 21.46
0.07 2.59 2.11 16.44 23.32
A mA mA mA mA
supply current in Standby CE=1, CLK = 12 MHz mode supply current in Stop mode supply current in Pause mode supply current in active streaming run mode CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz
Table 58.
Typical current consumption - sensor analogue binning SVGA- scaled QVGA RGB565 @ 15 fps
IAVDD IVDD Units VDD = 2.8V VDD = 1.8V VDD = 2.8V Description supply current in power down mode supply current in Standby mode supply current in Stop mode supply current in Pause mode supply current in active streaming run mode Test conditions
Symbol
IPD Istanby IStop IPause Irun
CE=0, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz CE=1, CLK = 12 MHz
2.34 0.0024 0.0024 0.58 29
0.05 2.41 1.95 13 19
0.07 2.59 2.1 14 20
A mA mA mA mA
106/118
VS6724
Electrical characteristics
6.4
External clock
The VS6724 requires an external clock. This clock is a CMOS digital input. The clock input is fail-safe in power down mode. Table 59. External clock
Range CLK Min. DC coupled square wave Clock frequency(1) 6.50 Typ. VDD 27 Max. V MHz Unit
1. The uwExternalClockFrequencyDenumerator and bExternalClockFrequencyDenominator registers must be configured to match the frequency supplied on the CLK pin.
6.5
Chip enable
CE is a CMOS digital input. The module is powered down when a logic 0 is applied to CE. See Section Figure 11.: Power up sequence for further information.
107/118
Electrical characteristics
VS6724
6.6
IC slave interface
VS6724 contains an IC-type interface using two signals: a bidirectional serial data line (SDA) and an input-only serial clock line (SCL). See PLL operation for detailed description of protocol.
Table 60.
Symbol
Serial interface voltage levels(1)
Standard mode Parameter Min. Hysteresis of Schmitt Trigger Inputs VDD > 2 V VDD < 2V LOW level output voltage (open drain) at 3mA sink current VDD > 2 V VDD < 2V HIGH level output voltage Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400 pF Pulse width of spikes which must be suppressed by the input filter Max. Min. Max. Fast mode Unit
VHYS
N/A N/A
N/A N/A
0.05 VDD 0.1 VDD
-
V V
VOL1 VOL3 VOH tOF tSP
0 N/A N/A N/A
0.4 N/A N/A 250 N/A
0 0 0.8 VDD 20+0.1Cb(2) 0
0.4 0.2 VDD
V V V
250 50
ns ns
1. Maximum VIH = VDDmax + 0.5 V 2. Cb = capacitance of one bus line in pF
Figure 40. Voltage level specification Input voltage levels Output voltage levels
VOH = 0.8 * VDD VIH = 0.7 * VDD
VIL = 0.3 * VDD
VOL = 0.2 * VDD
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VS6724 Table 61.
Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL VnH
Electrical characteristics Timing specification(1)
Standard mode Parameter Min. SCL clock frequency Hold time for a repeated start LOW period of SCL HIGH period of SCL Set-up time for a repeated start Data hold time (1) Data Set-up time (1) Rise time of SCL, SDA Fall time of SCL, SDA Set-up time for a stop Bus free time between a stop and a start Capacitive Load for each bus line Noise Margin at the LOW level for each connected device (including hysteresis) Noise Margin at the HIGH level for each connected device (including hysteresis) 0 4.0 4.7 4.0 4.7 300 250 4.0 4.7 0.1 VDD 0.2 VDD Max. 100 1000 300 400 Min. 0 0.6 1.3 0.6 0.6 300 100 20+0.1Cb(2) 20+0.1Cb(2) 0.6 1.3 0.1 VDD 0.2 VDD Max. 400 300 300 400 kHz s s s s ns ns ns ns s s pF V V Fast mode Unit
1. All values are referred to a VIHmin = 0.9 VDD and VILmax = 0.1 VDD 2. Cb = capacitance of one bus line in pF
109/118
Electrical characteristics Figure 41. Timing specification
SDA
VS6724
tSP tSU;STA SCL tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF tHD;STA
S START
tLOW
tHIGH
tr
tf
P STOP
S START
All values are referred to a VIHmin = 0.9 VDD and VILmax = 0.1 VDD
Figure 42. SDA/SCL rise and fall times
0.9 * VDD 0.9 * VDD
0.1 * VDD
0.1 * VDD
tr
tf
110/118
VS6724
Electrical characteristics
6.7
Parallel data interface timing
VS6724 contains a parallel data output port (D[7:0]) and associated qualification signals (HSYNC, VSYNC, PCLK and FSO). This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or bit-serial output configurations. The port is disabled (high impedance) upon reset. Figure 43. Parallel data output video timing
1/fPCLK tPCLKL PCLK polarity = 0 tDV D[0:7] HSYNC, VSYNC Valid tPCLKH
Table 62.
Symbol fPCLK tPCLKL tPCLKH tDV
Parallel data interface timings
Description PCLK frequency PCLK low width PCLK high width PCLK to output valid (1/2 * (1/fPCLK)) -1 (1/2 * (1/fPCLK)) -1 -1 Min. 80 (1/2 * (1/fPCLK)) +1 (1/2 * (1/fPCLK)) +1 1 Max. Unit MHz ns ns ns
111/118
Application circuit
VS6724
7
Application circuit
Figure 44. Application diagram
1.8V or 2.8V 2.8V
8 AVDD DIO[7:0] PCLK DVDD HSYNC VSYNC DVDD VS6724 2 GND SDA FSO GND 112/118 SCL 4.7KR Host
CE CLK
External Clock
Flashgun Driver / controller
VS6724
Application circuit
113/118
User precaution
VS6724
8
User precaution
As is common with many CMOS imagers the camera should not be pointed at bright static objects for long periods of time as permanent damage to the sensor may occur.
9
Package mechanical data
Figure 45 and Figure 46 details the package outline socket module VS6724.
114/118
VS6724
1 2 +0.10 8.00 - 0.05 5.55 0.10 A 3.84 3.45 0.10 6
3 4 7 8
5
A
1.4
B
0.8
B
C 7.65 at A
7.0
Figure 45. Package outline socket module VS6724
C
2.20 0.10
D
D
A
E
1.55 0.10
C
C (32 : 1)
Interpret drawing per BS308, 3RD Angle Projection Material All dimensions in mm Finish
Camera is compatible with SMK socket typre CLE9124-150F
E
REV. 1 2
DESCRIPTIO N Draft version for comment, 1st release under7976351 Updated to give compatibility with CLE9124-150F socket
DATE 03/04/2006 24/04/2006
Tolerances, unless otherwise stated
F
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
All dimensions in mm
Do Not Scale
Scale
F
STMicroelectronics
Sig. Date Part No. Title 724 Camera Outline Sheet
Linear 0 Place Decimals 0 0.10 1 Place Decimals 0.0 0.07 2 Place Decimals 0.00 0.05 Angular 0.25 degrees Diameter +0.10/-0.00 0.10 Position Surface Finish 1.6 microns
Drawn
7976351 6
Socket version
1 of 2 7 8
Package mechanical data
1 2
3
115/118
B
56.7
0.70 typ
C Pin 18
1.10
2.00 typ 1.30 0.90 Pin 1 Top Of Scene
3.52 @ datum A
E
0.90 1.80 2.70 3.60 4.50 5.40 6.30
3.50
3.05
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2 0.90 0.05 0.70 0.03 2.64 @ datunm A 4.40 @ datum A 3 4 6 7 8 Rev 1 5 A B H (40 : 1) 6 min. 7.88
68.0 44.1
1
Package mechanical data
A
Figure 46. Package outline socket module VS6724
C
D
H
A
D
Pin 6 Pad Layout
Interpret drawing per BS308, 3RD Angle Projection Material All dimensions in mm Finish
Pin 1 Pin 24
E
Tolerances, unless otherwise stated
Viewning cone and pyramid dimensions All dimensions are maximums
All dimensions in mm Do Not Scale
Scale
F
This drawing is the property of STMicroelectronics and will not be copied or loaned without the written permission of STMicroelectronics.
F
STMicroelectronics
Sig. Date Part No. Title Sheet
Linear 0 Place Decimals 0 1.0 1 Place Decimals 0.0 0.10 2 Place Decimals 0.00 0.03 Angular 0.25 degrees Diameter +0.10/-0.00 0.10 Position Surface Finish 1.6 microns
Drawn
7976351 6 7
VS6724
1 2
3
724 Camera Outline 8
VS6724
Ordering information
10
Ordering information
Table 63. Order codes
Package and packing SmOP2 - Socket version
Part number VS6724Q0FB
11
Revision history
Table 64.
Date 03-Jul-2007
Document revision history
Revision 1 Initial release. Changes
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VS6724
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